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features ? 8-bit microcontroller compatible with 8051 products ? enhanced 8051 architecture ? single clock cycle per byte fetch ? 12 clock per machine cy cle compatibility mode ? up to 20 mips throughput at 20 mhz clock frequency ? fully static operation: 0 hz to 20 mhz ? on-chip 2-cycle hardware multiplier ? 16x16 multiply?accumulate unit ? 256 x 8 internal ram ? on-chip 1152 bytes expanded ram (eram) ? software selectable size (0, 256, 512, 768, 1024 or 1152 bytes) ? dual data pointers ? 4-level interrupt priority ? nonvolatile program and data memory ? 24kb/32kb of in-system programmable (isp) flash program memory ? 512-byte user signature array ? endurance: 10,000 write/erase cycles ? serial interface for program downloading ? 2kb boot rom contains low level flash programming routines and a default serial bootloader ? peripheral features ? three 16-bit enhanced timer/counters ? seven 8-bit pwm outputs ? 16-bit programmable counter array ? high speed output , compare/capture ? pulse width modulation, watchdog timer capabilities ? enhanced uart with automatic ad dress recognition and framing error detection ? enhanced master/slave spi with double-buffered send/receive ? two wire interface 400k bit/s ? programmable watchdog timer with software reset ? 8 general-purpose interrupt and keyboard interface pins ? special microcontroller features ? dual oscillator support: crystal, 32 kh z crystal, 8 mhz inte rnal (at89lp51ic2) ? two-wire on-chip debug interface ? brown-out detection and power-on reset with power-off flag ? selectable polarity external reset pin ? low power idle and power-down modes ? interrupt recovery from power-down mode ? 8-bit clock prescaler ? i/o and packages ? up to 40 programmable i/o lines ? green (pb/halide-free) plcc 44, vqfp44, qfn44. pdip40 ? configurable i/o modes ? quasi-bidirectional (80c51 st yle), input-only (tristate) ? push-pull cmos output, open-drain ? operating conditions ? 2.4v to 5.5v v cc voltage range ?-40 c to 85c temperature range ? 0 to 20 mhz @ 2.4v?5.5v (single-cycle) 8-bit flash microcontroller with 24k/32k bytes program memory at89lp51rb2 at89lp51rc2 at89lp51ic2 preliminary 3722a?micro?10/11
2 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 1. pin configurations 1.1 44-lead tqfp/lqfp 1.2 44-lead plcc 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 (?mosi/cex2/miso) p1.5 (?miso/cex 3 /sck) p1.6 (?sck/cex4/mosi) p1.7 (dcl) rst (rxd) p 3 .0 (sda) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 (scl) p4.4 (ale) p4.5 (psen) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p1.4 (cex1/ss?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ss) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 vss (dda) p4. 3 (a8) p2.0 (a9) p2.1 (dac-/a10) p2.2 (dac+/a11) p2. 3 (ain0/a12) p2.4 ? spi in remap mode ? at89lp51id2 only 7 8 9 10 11 12 1 3 14 15 16 17 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 (?mosi/cex2/miso) p1.5 (?miso/cex 3 /sck) p1.6 (?sck/cex4/mosi) p1.7 (dcl) rst (rxd) p 3 .0 (sda) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 (scl) p4.4 (ale) p4.5 (psen) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) 6 5 4 3 2 1 44 4 3 42 41 40 18 19 20 21 22 2 3 24 25 26 27 28 (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 vss (dda) p4. 3 (a8) p2.0 (a9) p2.1 (dac-/a10) p2.2 (dac+/a11) p2. 3 (ain0/a12) p2.4 p1.4 (cex1/ss?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ss) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) ? spi in remap mode ? at89lp51id2 only
3 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 1.3 44-pad vqfn/qfn/mlf 1.4 40-pin pdip note: 1. the at 8 9lp51ic2 is not a v a il a ble in the pdip p a ck a ge 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 bottom pad s hould b e s oldered to ground note: ? spi in remap mode ? at89lp51id2 only (?mosi/cex2/miso) p1.5 (?miso/cex 3 /sck) p1.6 (?sck/cex4/mosi) p1.7 (dcl) rst (rxd) p 3 .0 (sda) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 (scl) p4.4 (ale) p4.5 (psen) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p1.4 (cex1/ss?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ss) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 gnd (dda) p4. 3 (a8) p2.0 (a9) p2.1 (da-/a10) p2.2 (da+/a11) p2. 3 (ain0/a12) p2.4 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 40 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 22 21 (t2) p1.0 (ss/t2ex) p1.1 (eci) p1.2 (cex0) p1. 3 (?ss/cex1) p1.4 (?mosi/cex2/miso) p1.5 (?miso/cex 3 /scl) p1.6 (?sck/cex4/mosi) p1.7 rst (rxd) p 3 .0 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 gnd vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.4 (ale) p4.5 (psen) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p2.4 (a12/ain0) p2. 3 (a11/dac+) p2.2 (a10/dac-) p2.1 (a9) p2.0 (a8) ?spi in remap mode
4 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 1.5 pin description table 1-1. atmel at 8 9lp51rb2/rc2/ic2 pin description pin number symbol type description vqfp vqfn plcc (1) pdip 176p1.5 i/o i/o i/o i/o p1.5 : user-config u r a ble i/o port 1 bit 5. miso : s pi m a ster-in/sl a ve-o u t. when config u red a s m a ster, this pin is a n inp u t. when config u red a ssl a ve, this pin is a n o u tp u t. mosi : s pi m a ster-o u t/sl a ve-in (rem a p mode). when config u red a s m a ster, this pin is a n o u tp u t. when config u red a s sl a ve, this pin is a n inp u t. d u ring in- s ystem progr a mming, this pin is a n inp u t. cex2 : c a pt u re/comp a re extern a l i/o for pca mod u le 2. 2 8 7p1.6 i/o i/o i/o i/o p1.6 : user-config u r a ble i/o port 1 bit 6. sck : s pi clock. when config u red a s m a ster, this pin is a n o u tp u t. when config u red a s sl a ve, this pin is a n inp u t. miso : s pi m a ster-in/sl a ve-o u t (rem a p mode). when config u red a s m a ster, this pin is a n inp u t. when config u red a ssl a ve, this pin is a n o u tp u t. d u ring in- s ystem progr a mming, this pin is a n o u tp u t. cex3 : c a pt u re/comp a re extern a l i/o for pca mod u le 3. 39 8 p1.7 i/o i/o i/o i/o p1.7 : user-config u r a ble i/o port 1 bit 7. mosi : s pi m a ster-o u t/sl a ve-in. when config u red a s m a ster, this pin is a n o u tp u t. when config u red a s sl a ve, this pin is a n inp u t. sck : s pi clock (rem a p mode). when config u red a s m a ster, this pin is a n o u tp u t. when config u red a s sl a ve, this pin is a n inp u t. d u ring in- s ystem progr a mming, this pin is a n inp u t. cex4 : c a pt u re/comp a re extern a l i/o for pca mod u le 4. 4109 r s t i/o i rst : extern a l reset inp u t (reset pol a rity depends on pol pin. s ee ?extern a l reset? on p a ge 53. ). the r s t pin c a n o u tp u t a p u lse when the intern a l w a tchdog reset or por is a ctive. dcl : s eri a l deb u g clock inp u t for on-chip deb u g interf a ce when ocd is en a bled. 51110p3.0 i/o i p3.0 : user-config u r a ble i/o port 3 bit 0. rxd : s eri a l port receiver inp u t. 612 p4.1 i/o i/o p4.1 : user-config u r a ble i/o port 4bit 1. sda : twi bidirection a l s eri a l d a t a line. 71311p3.1 i/o o p3.1 : user-config u r a ble i/o port 3 bit 1. txd : s eri a l port tr a nsmitter o u tp u t. 8 14 12 p3.2 i/o i p3.2 : user-config u r a ble i/o port 3 bit 2. int0 : extern a l interr u pt 0 inp u t or timer 0 g a te inp u t. 91513p3.3 i/o i p3.3 : user-config u r a ble i/o port 3 bit 3. int1 : extern a l interr u pt 1 inp u t or timer 1 g a te inp u t 10 16 14 p3.4 i/o i/o p3.4 : user-config u r a ble i/o port 3 bit 4. t1 : timer/co u nter 0 extern a l inp u t or o u tp u t. 11 17 15 p3.5 i/o i/o p3.5 : user-config u r a ble i/o port 3 bit 5. t1 : timer/co u nter 1 extern a l inp u t or o u tp u t. 12 1 8 16 p3.6 i/o o p3.6 : user-config u r a ble i/o port 3 bit 6. wr : extern a l memory interf a ce write s trobe ( a ctive-low). 13 19 17 p3.7 i/o o p3.7 : user-config u r a ble i/o port 3 bit 7. rd : extern a l memory interf a ce re a d s trobe ( a ctive-low). 14 20 1 8 p4.7 i/o o p4.7 : user-config u r a ble i/o port 4 bit 7. xtal2a : o u tp u t from inverting oscill a tor a mplifier a. it m a y be u sed a s a port pin if the intern a l rc oscill a tor or extern a l clock is selected a s the clock so u rce a. 15 21 19 p4.6 i/o i p4.6 : user-config u r a ble i/o port 4 bit 6. xtal1a : inp u t to the inverting oscill a tor a mplifier a a nd intern a l clock gener a tion circ u its. it m a y be u sed a s a port pin if the intern a l rc oscill a tor is selected a s the clock so u rce a.
5 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 16 22 20 gnd i gro u nd 17 23 p4.3 i/o i/o p4.3 : user-config u r a ble i/o port 4bit 3. dda : bidirection a l deb u g d a t a line for the on-chip deb u g interf a ce when ocd is en a bled. 1 8 24 21 p2.0 i/o o p2.0 : user-config u r a ble i/o port 2 bit 0. a8 : extern a l memory interf a ce address bit 8 . 19 25 22 p2.1 i/o o p2.1 : user-config u r a ble i/o port 2 bit 1. a9 : extern a l memory interf a ce address bit 9. 20 26 23 p2.1 i/o o o p2.2 : user-config u r a ble i/o port 2 bit 2. da- : dac neg a tive differenti a l o u tp u t. a10 : extern a l memory interf a ce address bit 10. 21 27 24 p2.3 i/o o o p2.3 : user-config u r a ble i/o port 2 bit 3. da+- : dac positive differenti a l o u tp u t. a11 : extern a l memory interf a ce address bit 11. 22 2 8 25 p2.4 i/o i o p2.4 : user-config u r a ble i/o port 2 bit 5. ain0 : an a log comp a r a tor inp u t 0. a12 : extern a l memory interf a ce address bit 12. 23 29 26 p2.5 i/o i o p2.5 : user-config u r a ble i/o port 2 bit 5. ain1 : an a log comp a r a tor inp u t 1. a13 : extern a l memory interf a ce address bit 13. 24 30 27 p2.6 i/o i o p2.6 : user-config u r a ble i/o port 2 bit 6. ain2 : an a log comp a r a tor inp u t 2. a14 : extern a l memory interf a ce address bit 14. 25 31 2 8 p2.7 i/o i o p2.7 : user-config u r a ble i/o port 2 bit 7. ain3 : an a log comp a r a tor inp u t 3. a15 : extern a l memory interf a ce address bit 15. 26 32 29 p4.5 i/o o p4.5 : user-config u r a ble i/o port 4 bit 5. psen : extern a l memory interf a ce progr a m s tore en a ble ( a ctive-low). 27 33 30 p4.4 i/o i/o p4.4 : user-config u r a ble i/o port 4 bit 4. ale : extern a l memory interf a ce address l a tch en a ble. 2 8 34 p4.0 i/o p4.0 : user-config u r a ble i/o port 4 bit 0. scl : twi s eri a l clock line. this line is a n o u tp u t in m a ter mode a nd a n inp u t in sl a ve mode. 29 35 31 pol i pol : reset pol a rity ( s ee ?extern a l reset? on p a ge 53. ) 30 36 32 p0.7 i/o i/o p0.7 : user-config u r a ble i/o port 0 bit 7. ad7 : extern a l memory interf a ce address/d a t a bit 7. 31 37 33 p0.6 i/o i/o i p0.6 : user-config u r a ble i/o port 0 bit 6. ad6 : extern a l memory interf a ce address/d a t a bit 6. adc6 : adc a n a log inp u t 6. 32 3 8 34 p0.5 i/o i/o i p0.5 : user-config u r a ble i/o port 0 bit 5. ad5 : extern a l memory interf a ce address/d a t a bit 5. adc5 : adc a n a log inp u t 5. 33 39 35 p0.4 i/o i/o i p0.4 : user-config u r a ble i/o port 0 bit 4. ad4 : extern a l memory interf a ce address/d a t a bit 4. adc4 : adc a n a log inp u t 4. 34 40 36 p0.3 i/o i/o i p0.3 : user-config u r a ble i/o port 0 bit 3. ad3 : extern a l memory interf a ce address/d a t a bit 3. adc3 : adc a n a log inp u t 3. table 1-1. atmel at 8 9lp51rb2/rc2/ic2 pin description pin number symbol type description vqfp vqfn plcc (1) pdip
6 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: 1. the at 8 9lp51ic2 is not a v a il a ble in the pdip p a ck a ge 2. overview the atmel ? at 8 9lp51rb2/rc2/ic2 is a low-power, high-perform a nce cmo s 8 -bit 8 051 micro- controller with 24/32 kb of in- s ystem progr a mm a ble fl a sh progr a m memory. the devices a re m a n u f a ct u red u sing atmel's high-density nonvol a tile memory technology a nd a re comp a tible with the ind u stry-st a nd a rd 8 0c51 instr u ction set. the at 8 9lp51rb2/rc2/ic2 is b u ilt a ro u nd a n enh a nced cpu core th a t c a n fetch a single byte from memory every clock cycle. in the cl a ssic 8 051 a rchitect u re, e a ch fetch req u ires 6 clock cycles, forcing instr u ctions to exec u te in 12, 24 or 4 8 clock cycles. in the at 8 9lp51rb2/rc2/ic2 cpu, st a nd a rd instr u ctions need only one to fo u r clock cycles providing six to twelve times more thro u ghp u t th a n the st a nd a rd 8 051. s eventy percent of instr u ctions need only a s m a ny clock cycles a s they h a ve bytes to exec u te, a nd most of the rem a ining instr u ctions req u ire only one a ddition a l clock. the enh a nced cpu core is c a p a ble of 20 mip s thro u ghp u t where a s the cl a ssic 8 051 cpu c a n deliver only 4 mip s a t the s a me c u rrent con- s u mption. conversely, a t the s a me thro u ghp u t a s the cl a ssic 8 051, the new cpu core r u ns a t a m u ch lower speed a nd thereby gre a tly red u cing power cons u mption a nd emi. the 35 41 37 p0.2 i/o i/o i p0.2 : user-config u r a ble i/o port 0 bit 2. ad2 : extern a l memory interf a ce address/d a t a bit 2. adc2 : adc a n a log inp u t 2. 36 42 3 8 p0.1 i/o i/o i p0.1 : user-config u r a ble i/o port 0 bit 1. ad1 : extern a l memory interf a ce address/d a t a bit 1. adc1 : adc a n a log inp u t 1. 37 43 39 p0.0 i/o i/o i p0.0 : user-config u r a ble i/o port 0 bit 0. ad0 : extern a l memory interf a ce address/d a t a bit 0. adc0 : adc a n a log inp u t 0. 3 8 44 40 vdd i su pply volt a ge 39 1 p4.2 i/o p4.2 : user-config u r a ble i/o port 4bit 2. xtal2b : o u tp u t from low-freq u ency inverting oscill a tor a mplifier b (at 8 9lp51ic2 only). it m a y be u sed a s a port pin if the intern a l rc oscill a tor or extern a l clock is selected a s the clock so u rce b. 40 2 1 p1.0 i/o i/o p1.0 : user-config u r a ble i/o port 1 bit 0. t2 : timer 2 extern a l inp u t or clock o u tp u t. xtal1b : inp u t to the low-freq u ency inverting oscill a tor a mplifier b a nd intern a l clock gener a tion circ u its. it m a y be u sed a s a port pin if the intern a l rc oscill a tor is selected a s the clock so u rce b. 41 3 2 p1.1 i/o i i p1.1 : user-config u r a ble i/o port 1 bit 1. t2ex : timer 2 extern a l c a pt u re/relo a d inp u t. ss : s pi s l a ve- s elect. 42 4 3 p1.2 i/o p1.2 : user-config u r a ble i/o port 1 bit 2. 43 5 4 p1.3 i/o i/o p1.3 : user-config u r a ble i/o port 1 bit 3. cex0 : c a pt u re/comp a re extern a l i/o for pca mod u le 0. 44 6 5 p1.4 i/o i i/o p1.4 : user-config u r a ble i/o port 1 bit 4. ss : s pi s l a ve- s elect (rem a p mode). this pin is a n inp u t for in- s ystem progr a mming cex1 : c a pt u re/comp a re extern a l i/o for pca mod u le 1. table 1-1. atmel at 8 9lp51rb2/rc2/ic2 pin description pin number symbol type description vqfp vqfn plcc (1) pdip
7 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary at 8 9lp51rb2/rc2/ic2 a lso incl u des a comp a tibility mode th a t will en a ble cl a ssic 12 clock per m a chine cycle oper a tion for tr u e timing comp a tibility with the atmel at 8 9c51rb2/rc2/ic2. the at 8 9lp51rb2/rc2/ic2 ret a ins a ll of the st a nd a rd fe a t u res of the at 8 9c51rb2/rc2/ic2, incl u ding: 24kb/32kb of in- s ystem progr a mm a ble fl a sh progr a m memory, 256 bytes of ram, 1152 bytes of exp a nded ram, u p to 40 i/o lines, three 16-bit timer/co u nters, a progr a mm a ble co u nter arr a y, a progr a mm a ble h a rdw a re w a tchdog timer, a keybo a rd interf a ce, a f u ll-d u plex enh a nced seri a l port, a seri a l peripher a l interf a ce ( s pi), on-chip cryst a l oscill a tor, a nd a fo u r- level, ten-vector interr u pt system. a block di a gr a m is shown in fig u re 2-1 . in a ddition, the atmel ? at 8 9lp51rb2/rc2/ic2 provides a two-wire interf a ce (twi) for u p to 400kb/s seri a l tr a nsfer; a 10-bit, 8 -ch a nnel an a log-to-digit a l converter (adc) with temper a t u re sensor a nd digit a l-to- a n a log (dac) mode; two a n a log comp a r a tors; a nd a n 8 mhz intern a l oscill a tor. s ome st a nd a rd fe a t u res on the at 8 9lp51rb2/rc2/ic2 a re enh a nced with new modes or oper- a tions. mode 0 of timer 0 or timer 1 a cts a s a v a ri a ble 9?16 bit timer/co u nter a nd mode 1 a cts a s a 16-bit au to-relo a d timer/co u nter. in a ddition, e a ch timer/co u nter m a y independently drive a n 8 -bit precision p u lse width mod u l a tion o u tp u t. mode 0 (synchrono u s mode) of the seri a l port a llows flexibility in the ph a se/pol a rity rel a tionship between clock a nd d a t a . the i/o ports of the at 8 9lp51rb2/rc2/ic2 c a n be independently config u red in one of fo u r oper a ting modes. in q ua si-bidirection a l mode, the ports oper a te a s in the cl a ssic 8 051. in inp u t- only mode, the ports a re trist a ted. p u sh-p u ll o u tp u t mode provides f u ll cmo s drivers a nd open- dr a in mode provides j u st a p u ll-down. unlike other 8 051s, this a llows port 0 to oper a te with on- chip p u ll- u ps if desired. the at 8 9lp51rb2/rc2/ic2 incl u des a n on-chip deb u g (ocd) interf a ce th a t a llows re a d-mod- ify-write c a p a bilities of th e system st a te a nd progr a m flow control, a nd progr a mming of the intern a l memories. the on-chip fl a sh m a y a lso be progr a mmed thro u gh the uart-b a sed boot- lo a der or the s pi-b a sed in- s ystem progr a mming interf a ce (i s p). the twi a nd ocd fe a t u res a re not a v a il a ble on the pdip p a ck a ge. the at 8 9lp51ic2 is a lso not a v a il a ble in the pdip. the fe a t u res of the at 8 9lp51rb2/rc2/ic2 m a ke it a powerf u l choice for a pplic a tions th a t need p u lse width mod u l a tion, high speed i/o, a nd co u nting c a p a bilities s u ch a s a l a rms, motor control, corded phones, a nd sm a rt c a rd re a ders.
8 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 2.1 block diagram figure 2-1. atmel at 8 9lp51rb2/rc2/ic2 block di a gr a m 2.2 system configuration the at 8 9lp51rb2/rc2/ic2 s u pports sever a l system config u r a tion options. nonvol a tile options a re set thro u gh u ser f u ses th a t m u st be progr a mmed thro u gh the fl a sh progr a mming interf a ce. vol a tile options a re controlled by softw a re thro u gh individ ua l bits of speci a l f u nction registers ( s frs). the at 8 9lp51rb2/rc2/ic2 m u st be properly config u red before correct oper a tion c a n occ u r. 2.2.1 fuse options t a ble 2-1 lists the f u sible options for the at 8 9lp51rb2/rc2/ic2. these options m a int a in their st a te even when the device is powered off. s ome m a y be ch a nged thro u gh the fl a sh api b u t others c a n only be ch a nged with a n extern a l device progr a mmer. for more inform a tion, see s ection 24.2 ?user config u r a tion f u ses? on p a ge 1 88 . fla s h code 24/ 3 2 kb port 2 configura b le i/o port 1 configura b le i/o uart spi timer 0 timer 1 watchdog timer cry s tal or re s onator port 4 configura b le i/o port 3 configura b le i/o timer 2 port 0 configura b le i/o ram 256 byte s xram interface 8051 single cycle cpu with 12-cycle compati b lity por bod dual data pointer s multiply accumulate (16 x 16) eram 1152 byte s key b oard interface pca boot rom 2kb on-chip de b ug internal 8 mhz rc o s cillator configura b le o s cillator a 10- b it adc/dac twi 7 dual analog comparator s cry s tal or re s onator configura b le o s cillator b (at89lp51ic2)
9 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 2.2.2 software options t a ble 2-2 lists some import a nt softw a re config u r a tion bits th a t a ffect oper a tion a t the system level. these c a n be ch a nged by the a pplic a tion softw a re b u t a re set to their def au lt v a l u es u pon a ny reset. most peripher a ls a lso h a ve m u ltiple config u r a tion bits th a t a re not listed here. table 2-1. user config u r a tion f u ses fuse name description clock s o u rce a s elects between the high s peed cryst a l oscill a tor, low power cryst a l oscill a tor, extern a l clock on xtal1a or intern a l rc oscill a tor for the so u rce of the system clock when oscill a tor a is selected. clock s o u rce b s elects between the 32 khz cryst a l oscill a tor, extern a l clock on xtal1b or intern a l rc oscill a tor for the so u rce of the system clock when oscill a tor b is selected (at 8 9lp51ic2 only). oscill a tor s elect s elects whether oscill a tor a or b is en a bled to boot the device. (at 8 9lp51ic2 only) x2 mode s elects the def au lt st a te of whether the clock so u rce is divided by two (x1) or not (x2) to gener a te the system clock. s t a rt- u p time s elects time-o u t del a y for the por/bod/pwd w a ke- u p period. comp a tibility mode config u res the cpu in 12-clock comp a tibility or single-cycle f a st exec u tion mode. xram config u r a tion config u res if a ccess to on-chip memories th a t a re m a pped to the extern a l d a t a memory a ddress sp a ce is en a bled/dis a bled by def au lt. bootlo a der j u mp bit en a bles or dis a bles the on-ship bootlo a der. on-chip deb u g en a ble en a bles or dis a bles on-chip deb u g. ocd m u st be en a bled prior to u sing a n in-circ u it deb u gger with the device. in- s ystem progr a mming en a ble en a bles or dis a bles in- s ystem progr a mming. user s ign a t u re progr a mming en a ble en a bles or dis a bles progr a mming of user s ign a t u re a rr a y. def au lt port s t a te config u res the def au lt port st a te a s inp u t-only mode (trist a ted) or q ua si-bidirection a l mode (we a kly p u lled high). low power mode en a bles or dis a bles power red u ction fe a t u res for lower system freq u encies. table 2-2. import a nt s oftw a re config u r a tion bits bit(s) sfr location description pxm0.y pxm1.y p0m0, p0m1, p1m0, p1m1, p2m0, p2m1, p3m0, p3m1, p4m0, p4m1 config u res the i/o mode of port x pin y to be one of inp u t-only, q ua si- bidirection a l, p u sh-p u ll o u tp u t or open-dr a in. the def au lt st a te is controlled by the def au lt port s t a te f u se a bove ckrl ckrl s elects the division r a tio between the oscill a tor a nd the system clock tp s 3-0 clkreg.7-4 s elects the division r a tio between the system clock a nd the timers ale s auxr.0 en a bles/dis a bles toggling of ale exram auxr.1 en a bles/dis a bles a ccess to on-chip memories th a t a re m a pped to the extern a l d a t a memory a ddress sp a ce w s 1-0 auxr.6-5 s elects the n u mber of w a it st a tes when a ccessing extern a l d a t a memory x s tk auxr1.4 config u res the h a rdw a re st a ck to be in ram or extr a ram enboot auxr1.5 en a bles/dis a bles a ccess to the on-chip fl a sh api
10 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 2.3 comparison to the atmel at89c51rb2/rc2/ic2 the atmel ? at 8 9lp51rb2/rc2/ic2 is p a rt of a f a mily of devices with enh a nced fe a t u res th a t a re f u lly bin a ry comp a tible with the 8 051 instr u ction set. the at 8 9lp51rb2/rc2/ic2 h a s two modes of oper a tions, comp a tibility mode a nd f a st mode. in comp a tibility mode the instr u ction timing, peripher a l beh a vior, s fr a ddresses, bit a ssignments a nd pin f u nctions a re identic a l to the existing atmel at 8 9c51rb2/rc2/ic2 prod u ct. addition a l enh a ncements a re tr a nsp a rent to the u ser a nd c a n be u sed if desired. f a st mode a llows gre a ter perform a nce, b u t with some dif- ferences in beh a vior. the m a jor enh a ncements from the at 8 9c51rb2/rc2/ic2 a re o u tlined in the following p a r a gr a phs a nd m a y be u sef u l to u sers migr a ting to the at 8 9lp51rb2/rc2/ic2 from older devices. a s u mm a ry of the differences between comp a tibility a nd f a st modes is given in t a ble 2-3 on p a ge 12 . s ee a lso the applic a tion note ?migr a ting from at 8 9c51rb2/rc2/ic2 to at 8 9lp51rb2/rc2/ic2.? 2.3.1 instruction execution in comp a tibility mode the atmel ? at 8 9lp51rb2/rc2/ic2 cpu u ses the six-st a te m a chine cycle of the st a nd a rd 8 051 where instr u ction bytes a re fetched every thre e system clock cycles. exec u tion times in this mode a re identic a l to the atmel at 8 9c51rb2/rc2/ic2. for gre a ter per- form a nce the u ser c a n en a ble f a st mode by dis a bling the comp a tibility f u se. in f a st mode the cpu fetches one code byte from memory every clock cycle inste a d of every three clock cycles. this gre a tly incre a ses the thro u ghp u t of the cpu. e a ch st a nd a rd instr u ction exec u tes in only one to fo u r clock cycles. s ee ?instr u ction s et su mm a ry? on p a ge 173 for more det a ils. any soft- w a re del a y loops or instr u ction-b a sed timing oper a tions m a y need to be ret u ned to a chieve the desired res u lts in f a st mode. 2.3.2 system clock the system clock so u rce is not limited to a cryst a l or extern a l clock. the system clock so u rce is select a ble between the cryst a l oscill a tor, a n extern a lly driven clock a nd a n intern a l 8 .0mhz rc oscill a tor for at 8 9lp51rb2/rc2 a nd clock so u rce a of at 8 9lp51ic2. clock so u rce b of at 8 9lp51ic2 is not limited to a 32 khz cryst a l. the clock so u rce b is select a ble between the 32 khz cryst a l oscill a tor, a n extern a lly driven clock a nd a n intern a l 8 .0mhz rc oscill a tor. unlike at 8 9c51ic2, the x2 a nd ckrl fe a t u res will a lso a ffect the o s cb so u rce. by def au lt in comp a tibility mode the system clock freq u ency is divided by 2 from the extern a lly s u pplied xtal1 freq u ency for comp a tibility with st a nd a rd 8 051s (12 clocks per m a chine cycle). the s ystem clock divider c a n sc a le the system clock vers u s the oscill a tor so u rce ( s ee s ection 6. 8 on p a ge 47 ). the divide-by-2 c a n be dis a bled to oper a te in x2 mode (6 clocks per m a chine cycle) or the clock m a y be f u rther divided to red u ce the oper a ting freq u ency. in f a st mode the clock divider def au lts to divide by 1. 2.3.3 reset the r s t pin of the at 8 9lp51rb2/rc2/ic2 h a s select a ble pol a rity u sing the pol pin (formerly ea ). when pol is high the r s t pin is a ctive high with a p u ll-down resistor a nd when pol is low the r s t pin is a ctive low with a p u ll- u p resistor. for existing at 8 9c51rb2/rc2/ic2 sockets where ea is tied to vdd, repl a cing at 8 9c51rb2/rc2/ic2 with at 8 9lp51rb2/rc2/ic2 will m a int a in the a ctive high reset. note th a t forcing extern a l exec u tion by tying ea low is not s u pported. the at 8 9lp51rb2/rc2/ic2 incl u des a n on-chip power-on reset a nd brown-o u t detector cir- c u it th a t ens u res th a t the device is reset from system power u p. in most c a ses a rc st a rt u p
11 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary circ u it is not req u ired on the r s t pin, red u cing system cost, a nd the r s t pin m a y be left u ncon- nected if a bo a rd-level reset is not present. 2.3.4 timer/counters a common presc a ler is a v a il a ble to divide the time b a se for timer 0, timer 1, timer 2 a nd the wdt. the tp s 3-0 bits in the clkreg s fr control the presc a ler ( t a ble 6- 8 on p a ge 47 ). in comp a tibility mode tp s 3-0 def au lts to 0101b, which c au ses the timers to co u nt once every m a chine cycle. the co u nting r a te c a n be a dj u sted line a rly from the system clock r a te to 1/16 of the system clock r a te by ch a nging tp s 3-0 . in f a st mode tp s 3-0 def au lts to 0000b, or the system clock r a te. tp s does not a ffect timer 2 in clock o u t or b au d gener a tor modes. in comp a tibility mode the s a mpling of the extern a l timer/co u nter pins: t0, t1, t2 a nd t2ex; a nd the extern a l interr u pt pins, int0 a nd int1 , is a lso controlled by the presc a ler. in f a st mode these pins a re a lw a ys s a mpled a t the system clock r a te. both timer 0 a nd timer 1 c a n toggle their respective co u nter pins, t0 a nd t1, when they over- flow by setting the o u tp u t en a ble bits in tconb. 2.3.5 interrupt handling f a st mode a llows for f a ster interr u pt response d u e to the shorter instr u ction exec u tion times. 2.3.6 keyboard interface the at 8 9lp51rb2/rc2/ic2 does not cle a r the keybo a rd fl a g register (kbf) a fter a re a d. e a ch bit m u st be cle a red in softw a re. this a llows the interr u pt to be gener a te once per fl a g when m u l- tiple fl a gs a re set, if desired. to mimic the old beh a vior the service ro u tine m u st cle a r the whole register. the keybo a rd c a n a lso s u pport gener a l edge-triggered interr u pts with the a ddition of the kbmod register. 2.3.7 serial port the timer presc a ler incre a ses the r a nge of a chiev a ble b au d r a tes when u sing timer 1 to gener- a te the b au d r a te in uart modes 1 or 3, incl u ding a n incre a se in the m a xim u m b au d r a te a v a il a ble in comp a tibility mode. addition a l fe a t u res incl u de au tom a tic a ddress recognition a nd fr a ming error detection. the shift register mode (mode 0) h a s been enh a nced with more control of the pol a rity, ph a se a nd freq u ency of the clock a nd f u ll-d u plex oper a tion. this a llows em u l a tion of m a ster seri a l peripher a l ( s pi) a nd two-wire (twi) interf a ces. 2.3.8 i/o ports the p0, p1, p2 a nd p3 i/o ports of the at 8 9lp51rb2/rc2/ic2 m a y be config u red in fo u r differ- ent modes. the def au lt setting depends on the trist a te-port user f u se. when the f u se is set a ll the i/o ports revert to inp u t-only (trist a ted) mode a t power- u p or reset. when the f u se is not a ctive, ports p1, p2 a nd p3 st a rt in q ua si-bidirection a l mode a nd p0 st a rts in open-dr a in mode. p4 a lw a ys oper a tes in q ua si-bidirection a l mode. p0 c a n be config u red to h a ve intern a l p u ll- u ps by pl a cing it in q ua si-bidirection a l or o u tp u t modes. this c a n red u ce system cost by removing the need for extern a l p u ll- u ps on port 0. the p4.4?p4.7 pins a re a ddition a l i/os th a t repl a ce the norm a lly dedic a ted ale, p s en, xtal1 a nd xtal2 pins of the at 8 9c51rb2/rc2/ic2. these pins c a n be u sed a s a ddition a l i/os depending on the config u r a tion of the clock a nd extern a l memory.
12 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 2.3.9 security the at 8 9lp51rb2/rc2/ic2 does not s u pport the extern a l a ccess pin (ea ). therefore it is not possible to exec u te from extern a l progr a m memory in a ddress r a nge 0000h?1fffh. when the third lockbit is en a bled (lock mode 4) extern a l progr a m exec u tion is dis a bled for a ll a ddresses a bove 1fffh. this differs from at 8 9c51rb2/rc2/ic2 where lock mode 4 prevents ea from being s a mpled low, b u t m a y still a llow extern a l exec u tion a t a ddresses o u tside the 8 k intern a l sp a ce. 2.3.10 programming the at 8 9lp51rb2/rc2/ic2 s u pports a richer comm a nd set for in- s ystem progr a mming (i s p). existing at 8 9c51rb2/rc2/ic2 progr a mmers sho u ld be a ble to progr a m the at 8 9lp51rb2/rc2/ic2 in byte mode. in p a ge mode the at 8 9lp51rb2/rc2/ic2 only s u pports progr a mming of a h a lf-p a ge of 64 bytes a nd therefore req u ires a n extr a a ddress byte a s com- p a red to at 8 9c51rb2/rc2/ic2. f u rthermore the device sign a t u re is loc a ted a t a ddresses 0000h, 0001h a nd 0003h inste a d of 0000h, 0100h a nd 0200h. table 2-3. comp a tibility mode vers u s f a st mode su mm a ry feature compatibility fast instr u ction fetch in s ystem clocks 3 1 instr u ction exec u tion time in s ystem clocks 6, 12, 1 8 or 24 1, 2, 3, 4 or 5 def au lt s ystem clock divisor 2 1 def au lt timer presc a ler divisor 6 1 pin sa mpling r a te (int0 , int1 , t0, t1, t2, t2ex) presc a ler r a te s ystem clock minim u m r s t inp u t p u lse in s ystem clocks 12 2
13 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3. memory organization the at 8 9lp51rb2/rc2/ic2 u ses a h a rv a rd architect u re with sep a r a te a ddress sp a ces for pro- gr a m a nd d a t a memory. the progr a m memory h a s a reg u l a r line a r a ddress sp a ce with s u pport for 64k bytes of directly a ddress a ble a pplic a tion code. the d a t a memory h a s 256 bytes of inter- n a l ram a nd 12 8 bytes of s peci a l f u nction register i/o sp a ce. the at 8 9lp51rb2/rc2/ic2 s u pports u p to 64k bytes of extern a l d a t a memory, with portions of the extern a l d a t a memory sp a ce implemented on chip a s nonvol a tile fl a sh d a t a memory. extern a l progr a m memory is s u pported for a ddresses a bove 32k in some config u r a tions. the memory a ddress sp a ces of the at 8 9lp51rb2/rc2/ic2 a re listed in t a ble 3-1 . note: 1. the size of the edata sp a ce is config u r a ble with the xr s bits in auxr. 3.1 program memory the at 8 9lp51rb2/rc2/ic2 cont a ins 24k/32k bytes of on-chip in- s ystem progr a mm a ble fl a sh memory for progr a mstor a ge, pl u s s u pport for u p to 40k/32k bytes of extern a l progr a m memory. the fl a sh memory h a s a n end u r a nce of a t le a st 10,000 write/er a se cycles a nd a minim u m d a t a retention time of 10 ye a rs. the reset a nd interr u pt vectors a re loc a ted within the first 8 3 bytes of progr a m memory (refer to t a ble 9-1 on p a ge 59 ). const a nt t a bles c a n be a lloc a ted within the entire 64k progr a m memory a ddress sp a ce for a ccess by the movc instr u ction. a m a p of the at 8 9lp51rb2/rc2/ic2 progr a m memory is shown in fig u re 3-1 . s ee s ection 24. ?fl a sh mem- ory progr a mming? on p a ge 1 8 5 for more inform a tion on progr a mming the fl a sh memory. table 3-1. at 8 9lp51rb2/rc2/ic2 memory address s p a ces name description range data directly a ddress a ble intern a l ram 00h?7fh idata indirectly a ddress a ble intern a l ram a nd st a ck sp a ce 00h?ffh s fr directly a ddress a ble i/o register sp a ce 8 0h?ffh edata on-chip extr a ram a nd extended st a ck sp a ce 0000h?03ffh (1) xdata extern a l d a t a memory 0000h?ffffh code on-chip nonvol a tile fl a sh progr a m memory (at 8 9lp51rb2) 0000h?5fffh on-chip nonvol a tile fl a sh progr a m memory (at 8 9lp51xc2) 0000h?7fffh xcode extern a l progr a m memory (at 8 9lp51rb2) 6000h?ffffh extern a l progr a m memory (at 8 9lp51xc2) 8 000h?ffffh s ig on-chip nonvol a tile fl a sh sign a t u re a rr a y 0000h?01ffh boot on-chip bootlo a der rom a nd fl a sh api f 8 00h?ffffh
14 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 3-1. progr a m memory m a p 3.1.1 external program memory the at 8 9lp51rb2/rc2/ic2 implements 24/32/32 kb of the progr a m memory sp a ce intern a lly. the at 8 9lp51rb2/rc2/ic2 does not s u pport forcing extern a l exec u tion u sing the ea pin; how- ever it does a llow for u p to 40/32/32 kb of extern a l progr a m memory to be m a pped into the u pper portions of the a ddress sp a ce. for at 8 9lp51rb2 a ddresses 6000h?ffffh a re m a pped to extern a l progr a m memory. for at 8 9lp51rc2/ic2 a ddresses 8 000h?ffffh a re m a pped to extern a l progr a m memory. the at 8 9lp51rb2/rc2/ic2 u ses the st a nd a rd 8 051 extern a l progr a m memory interf a ce with the u pper a ddress on port 2, the lower a ddress a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale a nd p s en strobes. progr a m memory a ddresses a re a lw a ys 16-bits wide. extern a l progr a m exec u tion s a crifices two f u ll 8 -bit ports, p0 a nd p2, to the f u nction of a ddressing the progr a m memory. fig u re 3-2 shows a h a rdw a re config u r a tion for a ccessing u p to 64k bytes of extern a l rom u sing a 16-bit line a r a ddress. port 0 serves a s a m u ltiplexed a ddress/d a t a b u s to the rom. the address l a tch en a ble strobe (ale) is u sed to l a tch the lower a ddress byte into a n extern a l reg- ister so th a t port 0 c a n be freed for d a t a inp u t/o u tp u t. port 2 provides the u pper a ddress byte thro u gho u t the oper a tion. p s en strobes the extern a l memory. fig u re 3-3 shows the timing of the extern a l progr a m memory interf a ce. ale is emitted a t a con- st a nt r a te of 1/3 of the system clock with a 1/3 d u ty cycle. p s en is emitted a t a simil a r r a te, b u t with 50% d u ty cycle. the new a ddress ch a nges in the middle of the ale p u lse for l a tching on the f a lling edge a nd is trist a ted a t the f a lling edge of p s en . the instr u ction d a t a is s a mpled from p0 a nd l a tched intern a lly d u ring the high ph a se of the clock prior to the rising edge of p s en . this timing a pplies to both comp a tibility a nd f a st modes. in comp a tibility mode there is no dif- ference in instr u ction timing between intern a l a nd extern a l exec u tion. 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array sigen=0 sigen=1 8000 7fff external program memory (xcode: 30kb) internal program memory (code: 32kb) 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array at89lp51rb2 enboot = 1 f800 f7ff boot rom (boot: 2kb) 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array at89lp51rb2 enboot = 0 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array 8000 7fff external program memory (xcode: 32kb) internal program memory (code: 32kb) at89lp51rc2/ic2 enboot = 1 at89lp51rc2/ic2 enboot = 0 f800 f7ff boot rom (boot: 2kb) 6000 5fff external program memory (xcode: 40kb) internal program memory (code: 24kb) 6000 5fff external program memory (xcode: 38kb) internal program memory (code: 24kb)
15 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 3-2. exec u ting from extern a l progr a m memory figure 3-3. extern a l progr a m memory fetches in order for f a st mode to fetch extern a lly, two w a it st a tes m u st be inserted for every clock cycle, incre a sing the instr u ction exec u tion time by a f a ctor of 3. however, d u e to other optimiz a tions, extern a l f a st mode instr u ctions m a y still be 1/4 to 1/2 f a ster th a n their comp a tibility mode eq u iv- a lents. note th a t if ale is a llowed to toggle in f a st mode, there is a possibility th a t when the cpu j u mps from intern a l to extern a l exec u tion a short p u lse m a y occ u r on ale a s shown in fig- u re 3-4 . the set u p time from the a ddress to the f a lling edge of ale rem a ins the s a me. however, this beh a vior c a n be a voided by setting the di s ale bit prior to a ny j u mp a bove the 8 k border. figure 3-4. intern a l/extern a l progr a m memory bo u nd a ry (f a st mode) at89lp external program memory instr. addr oe psen p 3 p2 ale p0 p1 latch clk ale psen float pcl out p0 pch out p2 pch out pch out data sampled pcl out pcl out data sampled data sampled clk ale disale=0 psen float p0 sfr out p0 p2 sfr out p2 pch out pch out pcl out pcl out data sampled short pulse ale disale=1 internal execution external execution
16 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3.1.2 sig in a ddition to the 24k/32k code sp a ce, the at 8 9lp51rb2/rc2/ic2 a lso s u pports a 512-byte user s ign a t u re arr a y a nd a 12 8 -byte atmel s ign a t u re arr a y th a t a re a ccessible by the cpu. the atmel s ign a t u re arr a y is initi a lized with the device id in the f a ctory. the user s ign a t u re arr a y is a v a il a ble for u ser identific a tion codes or const a nt p a r a meter d a t a . d a t a stored in the sign a t u re a rr a y is not sec u re. s ec u rity bits will dis a ble writes to the a rr a y; however, re a ds by a n extern a l device progr a mmer a re a lw a ys a llowed. the sign a t u res c a n be a ccessed with the fl a sh api f u nctions or low-level iap interf a ce. s ee s ection 24.4 ?in-applic a tion progr a mming (iap)? on p a ge 190 for more inform a tion. 3.2 internal data memory the at 8 9lp51rb2/rc2/ic2 cont a ins 256 bytes of gener a l s ram d a t a memory pl u s 12 8 bytes of i/o memory m a pped into a single 8 -bit a ddress sp a ce. access to the intern a l d a t a memory does not req u ire a ny config u r a tion. the intern a l d a t a memory h a s three a ddress sp a ces: data, idata a nd s fr; a s shown in fig u re 3-5 . s ome portions of extern a l d a t a memory a re a lso imple- mented intern a lly. s ee ?extern a l d a t a memory? below for more inform a tion. figure 3-5. intern a l d a t a memory m a p 3.2.1 data the first 12 8 bytes of ram a re directly a ddress a ble by a n 8 -bit a ddress (00h?7fh) incl u ded in the instr u ction. the lowest 32 bytes of data memory a re gro u ped into 4 b a nks of 8 registers e a ch. the r s 0 a nd r s 1 bits (p s w.3 a nd p s w.4) select which register b a nk is in u se. instr u c- tions u sing register a ddressing will only a ccess the c u rrently specified b a nk. the lower 12 8 bit a ddresses a re a lso m a pped into data a ddresses 20h?2fh. 3.2.2 idata the f u ll 256 byte intern a l ram c a n be indirectly a ddressed u sing the 8 -bit pointers r0 a nd r1. the first 12 8 bytes of idata incl u de the data sp a ce. the h a rdw a re st a ck is a lso loc a ted in the idata sp a ce. 3.2.3 sfr the u pper 12 8 direct a ddresses ( 8 0h?ffh) a ccess the i/o registers. i/o registers on at 8 9lp devices a re referred to a s s peci a l f u nction registers. the s frs c a n only be a ccessed thro u gh direct a ddressing. all s fr loc a tions a re not implemented. s ee s ection 4. for a listed of a v a il a ble s frs. ffh upper 128 80h 7fh lower 128 0 accessible by direct addressing ffh 80h accessible by direct and indirect addressing special function registers ports status and control bits registers stack pointer accumulator (etc.) timers accessible by indirect addressing only idata sfr data/idata
17 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3.3 external data memory at 8 9lp microcontrollers s u pport a 16-bit extern a l memory a ddress sp a ce for u p to 64k bytes of extern a l d a t a memory (xdata). the extern a l memory sp a ce is a ccessed with the movx instr u ctions. s ome intern a l d a t a memory reso u rces a re m a pped into portions of the extern a l a ddress sp a ce a s shown in fig u re 3-6 . these memory sp a ces m a y req u ire config u r a tion before the cpu c a n a ccess them. the at 8 9lp51rb2/rc2/ic2 incl u des 1152 bytes of on-chip extr a ram (edata). 3.3.1 xdata the extern a l d a t a memory sp a ce c a n a ccommod a te u p to 64kb of extern a l memory. the at 8 9lp51rb2/rc2/ic2 u ses the st a nd a rd 8 051 extern a l d a t a memory interf a ce with the u pper a ddress byte on port 2, the lower a ddress byte a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr strobes. xdata c a n be a ccessed with both 16-bit (movx @dptr) a nd 8 -bit (movx @ri) a ddresses. s ee s ection 3.3.2 on p a ge 1 8 for more det a ils of the extern a l memory interf a ce. s ome intern a l d a t a memory sp a ces a re m a pped into portions of the xdata a ddress sp a ce. in this c a se the lower a ddress r a nges will a ccess intern a l reso u rces inste a d of extern a l memory. addresses a bove the r a nge implemented intern a lly will def au lt to xdata. the at 8 9lp51rb2/rc2/ic2 s u pports u p to 60?62k bytes of extern a l memory when u sing the inter- n a lly m a pped memories. s etting the extram bit (auxr.1) to one will force a ll movx instr u ctions to a ccess the entire 64kb xdata reg a rdless of their a ddress ( s ee ?auxr ? a u xil- i a ry control register? on p a ge 19 ). figure 3-6. extern a l d a t a memory m a p extra ram (edata: 1kb) 03ff flash program (code: 32kb) 0000 0400 ffff external data (xdata: 64kb) external data (xdata: 62kb) ffff 7fff exram = 1 xrs = x fps = x exram = 0 xrs = 011b fps = 0 exram = 0 xrs = x fps = 1
18 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3.3.2 external data memory interface the at 8 9lp51rb2/rc2/ic2 u ses the st a nd a rd 8 051 extern a l d a t a memory interf a ce with the u pper a ddress on port 2, the lower a ddress a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr strobes. the interf a ce m a y be u sed in two different config u r a tions depending on which type of movx instr u ction is u sed to a ccess xdata. fig u re 3-7 shows a h a rdw a re config u r a tion for a ccessing u p to 64k bytes of extern a l ram u sing a 16-bit line a r a ddress. port 0 serves a s a m u ltiplexed a ddress/d a t a b u s to the ram. the address l a tch en a ble strobe (ale) is u sed to l a tch the lower a ddress byte into a n extern a l reg- ister so th a t port 0 c a n be freed for d a t a inp u t/o u tp u t. port 2 provides the u pper a ddress byte thro u gho u t the oper a tion. the movx @dptr instr u ctions u se line a r address mode. figure 3-7. extern a l d a t a memory 16-bit line a r address mode fig u re 3- 8 shows a h a rdw a re config u r a tion for a ccessing 256-byte blocks of extern a l ram u sing a n 8 -bit p a ged a ddress. port 0 serves a s a m u ltiplexed a ddress/d a t a b u s to the ram. the ale strobe is u sed to l a tch the a ddress byte into a n extern a l register so th a t port 0 c a n be freed for d a t a inp u t/o u tp u t. the port 2 i/o lines (or other ports) c a n provide control lines to p a ge the mem- ory; however, this oper a tion is not h a ndled au tom a tic a lly by h a rdw a re. the softw a re a pplic a tion m u st ch a nge the port 2 register when a ppropri a te to a ccess different p a ges. the movx @ri instr u ctions u se p a ged address mode. figure 3-8. extern a l d a t a memory 8 -bit p a ged address mode note th a t prior to u sing the extern a l memory interf a ce, wr (p3.6) a nd rd (p3.7) m u st be config- u red a s o u tp u ts. s ee s ection 12.1 ?port config u r a tion? on p a ge 69 . p0 a nd p2 a re config u red au tom a tic a lly to p u sh-p u ll o u tp u t mode when o u tp u tting a ddress or d a t a a nd p0 is au tom a tic a lly trist a ted when inp u tting d a t a reg a rdless of the port config u r a tion. the port 0 config u r a tion will determine the idle st a te of port 0 when not a ccessing the extern a l memory. p1 p0 ale p2 rd p 3 wr at89lp data latch external data memory we addr oe p1 p0 i/o ale p2 rd p 3 wr at89lp data latch external data memory we addr pag e bits oe
19 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary fig u re 3-9 a nd fig u re 3-10 show ex a mples of extern a l d a t a memory write a nd re a d cycles, respectively. the a ddress on p0 a nd p2 is st a ble a t the f a lling edge of ale. the idle st a te of ale is controlled by di s ale (auxr.0). when di s ale = 0 the ale toggles a t a const a nt r a te when not a ccessing extern a l memory. when di s ale = 1 the ale is we a kly p u lled high. di s ale m u st be one in order to u se p4.4 a s a gener a l-p u rpose i/o. the w s bits in auxr c a n extended the rd a nd wr strobes by 1, 2 or 3 cycles a s shown in fig u res 3-13, 3-14 a nd 3-15. if a longer strobe is req u ired, the a pplic a tion c a n sc a le the system clock with the clock divider to meet the req u irements ( s ee s ection 6. 8 on p a ge 47 ). notes: 1. w s 1 is only a v a il a ble in f a st mode. w s 1 is forced to 0 in comp a tibility mode. table 3-2. auxr ? a u xili a ry control register auxr = 8 eh reset v a l u e = 0000 10x0b not bit address a ble dpu w s 1 (1) w s 0xr s 2xr s 1xr s 0 extram ao bit76543210 symbol function dpu dis a ble we a k p u ll- u p. when dpu = 0 a ll i/o ports in q ua si-bidirection a l mode h a ve their we a k p u ll- u p en a bled. when dpu = 1 a ll i/o ports in q ua si-bidirection a l mode h a ve their we a k p u ll- u p dis a bled to red u ce power cons u mption. w s 1-0 w a it s t a te s elect. determines the n u mber of w a it st a tes inserted into extern a l memory a ccesses. w s 1 w s 0 w a it s t a tes rd / wr s trobe width ale to rd / wr s et u p 000 1 x t cyc (f a st); 3 x t cyc (comp a tibility) 1 x t cyc (f a st); 1.5 x t cyc (comp a tibility) 011 2 x t cyc (f a st); 15 x t cyc (comp a tibility) 1 x t cyc (f a st); 1.5 x t cyc (comp a tibility) 102 2 x t cyc (f a st) 2 x t cyc (f a st) 113 3 x t cyc (f a st) 2 x t cyc (f a st) xr s 2-0 xram s ize. s elects the size of the on-chip extr a ram (edata) xr s 2 xr s 1 xr s 0 edata s ize (bytes) address r a nge 0 0 0 256 0000h?00ffh 0 0 1 512 0000h?01ffh 010 76 8 (def au lt) 0000h?02ffh 0 1 1 1024 0000h?03ffh 1 0 0 1152 0000h?047fh 101 reserved 11? reserved extram extern a l ram en a ble. when extram = 0, movx instr u ctions c a n a ccess the intern a lly m a pped portions of the a ddress sp a ce (extr a ram). accesses to a ddresses a bove intern a lly m a pped memory will a ccess extern a l memory. s et extram = 1 to byp a ss the intern a l memory a nd m a p the entire 64kb a ddress sp a ce to extern a l memory. the def au lt st a te of extram is set by a u ser config u r a tion f u se. s ee s ection 24.2 on p a ge 1 88 . di s ale ale o u tp u t. when ao = 0 the ale p u lse is a ctive a t 1/3 of the system clock freq u ency in comp a tibility mode a nd 1/2 of the system clock freq u ency in f a st mode. when ao = 1 the ale is in a ctive (high) u nless a n extern a l memory a ccess occ u rs. ao m u st be set to u se p4.4 a s a gener a l i/o.
20 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 3-9. f a st mode extern a l d a t a memory write cycle (w s =00b) figure 3-10. f a st mode extern a l d a t a memory re a d cycle (w s =00b) figure 3-11. comp a tibility mode extern a l d a t a memory write cycle (w s 0=0) s1 s2 s 3 s4 clk ale wr dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out s1 s2 s 3 s4 clk ale rd float data sampled dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 s4 s5 s6 s1 clk ale wr dpl or ri out p0 sfr pcl or p0 sfr p0 pch or p2 sfr pch or p2 sfr dph or p2 out p2 data out s2 s 3 s4 s5
21 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 3-12. comp a tibility mode extern a l d a t a memory re a d cycle (w s 0=0) figure 3-13. movx with one w a it s t a te (w s =01b) figure 3-14. movx with two w a it s t a tes (w s =10b) clk ale rd float data sampled dpl or ri out p0 sfr pcl or p0 sfr p0 pch or p2 sfr pch or p2 sfr dph or p2 out p2 s4 s5 s6 s1 s2 s 3 s4 s5 s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out s4 rd dpl out p0 sfr p0 sfr p0 float s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float s4
22 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 3-15. movx with three w a it s t a tes (w s =11b) 3.4 extra ram (edata) the extr a ram is a portion of the extern a l memory sp a ce implemented a s a n intern a l 2k byte au xili a ry ram. the extr a ram is m a pped into the edata sp a ce a t the bottom of the extern a l memory a ddress sp a ce, from 0000h to 07ffh, when extram = 0 (auxr.1). the size of edata c a n be red u ced by the xr s bits in auxr ( s ee t a ble 3-2 ). movx instr u ctions to this a ddress r a nge will a ccess the intern a l extr a ram. edata c a n be a ccessed with both 16-bit (movx @dptr) a nd 8 -bit (movx @ri) a ddresses. when 8 -bit a ddresses a re u sed, the page register (0f6h) s u pplies the u pper a ddress bits. the page register bre a ks edata into eight 256-byte p a ges. a p a ge c a nnot be specified independently for movx @r0 a nd movx @r1. s etting page a bove 07h en a bles xdata a ccess, b u t does not ch a nge the v a l u e of port 2. when 16-bit a ddresses a re u sed (dptr), the eee bit (eecon.1) m u st a lso be zero to a ccess edata. movx instr u ctions to edata req u ire a minim u m of 2 clock cycles. s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float w 3 s4 table 3-3. pag e ? edata p a ge register pa g e = f 6 h reset v a l u e = 0000 0000b not bit address a ble ? ? ? ? page.3 page.2 page.1 page.0 bit76543210 symbol function pag e 7-0 s elects which 256-byte p a ge of edata is c u rrently a ccessible by movx @ri instr u ctions when page < 0 8 h. any page v a l u e between 0 8 h a nd ffh will selected xdata; however, this v a l u e will not be o u tp u t on p2.
23 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3.5 extended stack the at 8 9lp51rb2/rc2/ic2 provides a n extended st a ck sp a ce for a pplic a tions req u iring a ddi- tion a l st a ck memory. by def au lt the st a ck is loc a ted in the 256-byte idata sp a ce of intern a l d a t a memory. the idata st a ck is referenced solely by the 8 -bit s t a ck pointer ( s p: 8 1h). s etting the x s tk bit in auxr1 (see t a ble 5-6 ) en a bles the extended st a ck. the extended st a ck resides in the edata sp a ce for u p to 2kb of st a ck memory. the extended st a ck is referenced by a n 11-bit pointer formed from s p a nd the three l s bs of the extended s t a ck pointer ( s px: efh) a s shown in fig u re 3-16 . s p is sh a red between both st a cks. note th a t the st a nd a rd idata st a ck will not overflow to the edata st a ck or vice vers a . the st a ck a nd extended st a ck a re m u t ua lly excl u sive a nd s px is ignored when xt s k=0. an a pplic a tion choosing to switch between st a cks by tog- gling x s tk m u st m a int a in sep a r a te copies of s p for u se with e a ch st a ck sp a ce. interr u pts sho u ld be dis a bled while sw a pping copies of s p in s u ch a n a pplic a tion to prevent illeg a l st a ck a ccesses. all interr u pt c a lls a nd pu s h, pop, acall, lcall, ret a nd reti instr u ctions will inc u r a one or two-cycle pen a lty while the extended st a ck is en a bled, depending on the n u mber of st a ck a ccess in e a ch instr u ction. the extended st a ck m a y only exist within the intern a l edata sp a ce; it c a nnot be pl a ced in xdata. the st a ck will contin u e to u se edata even if edata is dis a bled by setting exrram = 1. figure 3-16. s t a ck config u r a tions 7 0 00h ffh i data (256) sp 7 0 00h 7ffh e data (2k) sp 20 spx xstk = 0 xstk = 1
24 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 4. special function registers a m a p of the on-chip memory a re a c a lled the s peci a l f u nction register ( s fr) sp a ce is shown in t a ble 4-1 . note th a t not a ll of the a ddresses a re occ u pied, a nd u nocc u pied a ddresses m a y not be imple- mented on the chip. re a d a ccesses to these a ddresses will in gener a l ret u rn r a ndom d a t a , a nd write a ccesses will h a ve a n indetermin a te effect. user softw a re sho u ld not write to these u nlisted loc a tions, since they m a y be u sed in f u t u re prod u cts to invoke new fe a t u res. notes: 1. all s frs in the left-most col u mn a re bit- a ddress a ble. 2. reset v a l u e is 1111 1111b when trist a te-port f u se is en a bled a nd 0000 0000b when dis a bled. 3. reset v a l u e is 0101 0010b when comp a tibility mode is en a bled a nd 0000 0000b when dis a bled. table 4-1. atmel at 8 9lp51rb2/rc2/ic2 s fr m a p a nd reset v a l u es 8 9abcdef 0f 8 h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 0ffh 0f0h b 0000 0000 rl0 0000 0000 rl1 0000 0000 rh0 0000 0000 rh1 0000 0000 pag e 0000 0000 bx 0000 0000 0f7h 0e 8 h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 s px xxxx x000 0efh 0e0h acc 0000 0000 ax 0000 0000 d s pr 0000 0000 fird 0000 0000 macl 0000 0000 mach 0000 0000 p0m0 (2) p0m1 0000 0000 0e7h 0d 8 h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 0dfh 0d0h p s w 0000 0000 fcon xxxx 0000 eecon 0000 0000 dplb 0000 0000 dphb 0000 0000 p1m0 (2) p1m1 0000 0000 0d7h 0c 8 ht2con 0000 0000 t2mod 0000 0000 rcap2l 0000 000 rcap2h 0000 0000 tl2 0000 000 th2 0000 0000 p2m0 (2) p2m1 0000 0000 0cfh 0c0h p4 1111 1111 s pcon 0001 0100 s p s ta 0000 0000 s pdat xxxx xxxx p3m0 (2) p3m1 0000 0000 0c7h 0b 8 h ipl0 xx00 0000 s aden 0000 0000 aref 0000 0000 p4m0 (2) p4m1 0000 0000 0bfh 0b0h p3 1111 1111 ien1 xxxx 0000 ipl1 xxxx 0000 iph1 xxxx 0000 iph0 xx00 0000 0b7h 0a 8 h ien0 0x00 0000 s addr 0000 0000 ac s rb 0000 0000 dadl 0000 0000 dadh 0000 0000 clkreg 0101 xxxx ckcon1 xxxx xxx0 0afh 0a0h p2 1111 1111 dpcf 0000 xxxx auxr1 0000 00x0 ac s ra 0000 0000 dadc 0000 0000 dadi 0000 0000 wdtr s t (write-only) wdtprg 0000 0xx0 0a7h 9 8 h s con 0000 0000 s buf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbl s 0000 0000 kbe 0000 0000 kbf 0000 0000 kbmod 0000 0000 9fh 90h p1 1111 1111 tconb 0010 0100 bm s el xxxx xxx0 ss con 0000 0000 ss c s 1111 1000 ss dat 1111 1111 ss adr 1111 1110 ckrl 1111 1111 97h 88 h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0000 0000 ckcon0 0000 0000 8 fh 8 0h p0 1111 1111 s p 0000 0111 dpl 0000 0000 dph 0000 0000 ck s el xxxx xxx0 o s ccon xxxx x001 pcon 000x 0000 8 7h 01234567
25 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: 1. present on at 8 9lp51ic2 only table 4-2. c51 core s frs mnemonicaddname 76543210 acc e0h acc u m u l a tor b f0h b register p s w d0h progr a m s t a t u s word cy ac f0 r s 1r s 0ov f1 p s p 8 1h s t a ck pointer s px efh extended s t a ck pointer ???? s p11 s p10 s p9 s p 8 dpl 8 2h d a t a pointer low byte dph 8 3h d a t a pointer high byte dplb d4h altern a te d a t a pointer low byte dphb d5h altern a te d a t a pointer high byte pag e f 6 h e r a m p a ge register ???? table 4-3. digit a l s ign a l processing s frs mnemonicaddname 76543210 ax e1h extended acc u m u l a tor bx f7h extended b register d s pr e2h d s p control register mrw1 mrw0 s mlb s mla cbe1 cbe0 mvcd dprb fird e3h fifo depth macl e4h mac low byte mach e5h mac high byte table 4-4. s ystem m a n a gement s frs mnemonicaddname 76543210 pcon 8 7h power control s mod1 s mod0 pwdex pof gf1 gf0 pd idl auxr 8 eh a u xili a ry register 0 dpu w s 1w s 0/m0 xr s 2xr s 1xr s 0 extram ao auxr1 a2h a u xili a ry register 1 ? ? enboot x s tk gf3 0 ? dp s dpcf a1h d a t a pointer config register dpu1 dpu0 dpd1 dpd0 ? ? ? ? ckrl 97h clock relo a d register ckckon0 8 fh clock control register 0 twix2 wdtx2 pcax2 s ix2 t2x2 t1x2 t0x2 x2 ckckon1afhclock control register 1 ??????? s pix2 ck s el (1) 8 5h clock s election register ???????ck s clkreg aeh clock register tp s 3tp s 2tp s 1tp s 0? ? ? ? o s ccon (1) 8 5h oscill a tor control register ????? s clkt0 oscben oscaen
26 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 4-5. interr u pt s frs mnemonicaddname 76543210 ien0 a 8 h interr u pt en a ble control 0 ea ec et2 e s et1 ex1 et0 ex0 ien1 b1h interr u pt en a ble control 1 ? ? eadc ecmp ? e s pi etwi ekb iph0 b7h interr u pt priority control high 0 ip1d ppch pt2h ph s pt1h px1h pt0h px0h ipl0 b 8 h interr u pt priority control low 0 ip0d ppcl pt2l pl s pt1l px1l pt0l px0l iph1 b3h interr u pt priority control high 1 ip3d ? padl pcmpl ? s pih ptwl pkbh ipl1 b2h interr u pt priority control low 1 ip2d ? padh pcmph ? s pil ptwh pkbl table 4-6. port s frs mnemonicaddname 76543210 p0 8 0h 8 -bit port 0 p1 90h 8 -bit port 1 p2 a0h 8 -bit port 2 p3 b0h 8 -bit port 3 p4 c0h 8 -bit port 4 p0m0 e6h port 0 mode 0 p0m1 e7h port 0 mode 1 p1m0 d6h port 1 mode 0 p1m1 d7h port 1 mode 1 p2m0 ceh port 2 mode 0 p2m1 cfh port 2 mode 1 p3m0 c6h port 3 mode 0 p3m1 c7h port 3 mode 1 p4m0 beh port 4 mode 0 p4m1 bfh port 4 mode 1 table 4-7. s eri a l i/o port s frs mnemonicaddname 76543210 s con 9 8 h s eri a l control fe/ s m0 s m1 s m2 ren tb 8 rb 8 ti ri s buf 99h s eri a l d a t a b u ffer s aden b9h s l a ve address m a sk s addr a9h s l a ve address bdrcon 9bh b au d r a te control ? ? ? brr tbck rbck s pd s rc brl 9ah b au d r a te relo a d
27 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 4-8. timer s frs mnemonicaddname 76543210 tcon 88 htimer/co u nter 0 a nd 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 8 9h timer/co u nter 0 a nd 1 modes gate1 c/t1 m11 m01 gate0 c/t0 m10 m00 tconb 91h timer/co u nter 0 a nd 1 mode b tl0 8 ah timer/co u nter 0 low byte th0 8 ch timer/co u nter 0 high byte tl1 8 bh timer/co u nter 1 low byte th1 8 dh timer/co u nter 1 high byte rl0 f2h timer/co u nter 0 relo a d low rh0 f3h timer/co u nter 0 relo a d high rtl1 f4h timer/co u nter 1 relo a d low rh1 f5h timer/co u nter 1 relo a d high wdtr s ta6hw a tchdog timer reset wdtprg a7h w a tchdog timer progr a mwdtovf s wr s twdtenwdidledi s rtowto2wto1wto0 t2con c 8 htimer/co u nter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 t2mod c9h timer/co u nter 2 mode ??????t2oedcen rcap2h cbh timer/co u nter 2 relo a d/c a pt u re high byte rcap2l cah timer/co u nter 2 relo a d/c a pt u re low byte th2 cdh timer/co u nter 2 high byte tl2 cch timer/co u nter 2 low byte table 4-9. s pi controller s frs mnemonicaddname 76543210 s pcon c3h s pi control s pr2 s pen ss di s m s tr cpol cpha s pr1 s pr0 s p s ta c 4 h s pi s t a t u s s pif wcol ss err modf txe dord remap tbie s pdat c5h s pi d a t as pd7 s pd6 s pd5 s pd4 s pd3 s pd2 s pd1 s pd0 table 4-10. twi controller s frs mnemonicaddname 76543210 ss con 93h s ynchrono u s s eri a l control ss cr2 ss pe sss ta sss to ss i ss aa ss cr1 ss cr0 ss c s 94h s ynchrono u s s eri a l s t a t u s ss c4 ss c3 ss c2 ss c1 ss c0 0 0 0 ss dat 95h s ynchrono u s s eri a l d a t a ss adr 96h s ynchrono u s s eri a l address ss a7 ss a6 ss a5 ss a4 ss a3 ss a2 ss a1 ss gc
28 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 4-11. keybo a rd interf a ce s frs mnemonicaddname 76543210 kbl s 9ch keybo a rd level s elector kbl s 7 kbl s 6 kbl s 5 kbl s 4 kbl s 3 kbl s 2 kbl s 1 kbl s 0 kbe 9dh keybo a rd inp u t en a ble kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 kbf 9eh keybo a rd fl a g register kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 kbmod 9fh keybo a rd mode register kbm7 kbm6 kbm5 kbm4 kbm3 kbm2 kbm1 kbm0 table 4-12. fl a sh memory s fr mnemonicaddname 76543210 fcon d2h fl a sh control register fpl3 fpl2 fpl1 fpl0 fp s fmod1 fmod0 fbu s y eecon d2h eeprom control register fout aer s ldpg flge inhibit err eee eebu s y table 4-13. an a log comp a r a tor s frs mnemonicaddname 76543210 ac s ra a3h comp a r a tor a control register c s a1 c s a0 cona cfa cena cma cma1 cma0 ac s rb abh comp a r a tor b control register c s b1 c s b0 conb cfb cenb cmb cmb1 cmb0 aref bdh comp a r a tor reference register cmpb cmpa rfb1 rfb0 cc s 1cc s 0 rfa1 rfa0 table 4-14. adc controller s frs mnemonicaddname 76543210 dadc a4h dac/adc control register adif go/b s y dac adce ladj ack2 ack1 ack0 dadi a5h dac/adc inp u t register acon iref trg1 trg0 diff ac s 2ac s 1ac s 0 dadl ach dac/adc d a t a low register dadh adh dac/adc d a t a high register table 4-15. pca s frs mnemo -nicaddname 76543210 ccon d 8 h pca timer/co u nter control cf cr ? ccf4 ccf3 ccf2 ccf1 ccf0 cmod d9h pca timer/co u nter mode cidl wdte ? ? ? cp s 1cp s 0ecf cl e9h pca timer/co u nter low byte ch f9h pca timer/co u nter high byte ccapm0 dah pca timer/co u nter mode 0 ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 ccapm1 dbh pca timer/co u nter mode 1 ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 ccapm2 dch pca timer/co u nter mode 2 ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2 ccapm3 ddh pca timer/co u nter mode 3 ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3
29 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ccapm4 deh pca timer/co u nter mode 4 ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 ccap0h fah pca comp a re c a pt u re mod u le 0 h ccap0h7 ccap0h6 ccap0h5 ccap0h4 ccap0h3 ccap0h2 ccap0h1 ccap0h0 ccap1h fbh pca comp a re c a pt u re mod u le 1 h ccap1h7 ccap1h6 ccap1h5 ccap1h4 ccap1h3 ccap1h2 ccap1h1 ccap1h0 ccap2h fch pca comp a re c a pt u re mod u le 2 h ccap2h7 ccap2h6 ccap2h5 ccap2h4 ccap2h3 ccap2h2 ccap2h1 ccap2h0 ccap3h fdh pca comp a re c a pt u re mod u le 3 h ccap3h7 ccap3h6 ccap3h5 ccap3h4 ccap3h3 ccap3h2 ccap3h1 ccap3h0 ccap4h feh pca comp a re c a pt u re mod u le 4 h ccap4h7 ccap4h6 ccap4h5 ccap4h4 ccap4h3 ccap4h2 ccap4h1 ccap4h0 ccap0l eah pca comp a re c a pt u re mod u le 0 l ccap0l7 ccap0l6 ccap0l5 ccap0l4 ccap0l3 ccap0l2 ccap0l1 ccap0l0 ccap1l ebh pca comp a re c a pt u re mod u le 1 l ccap1l7 ccap1l6 ccap1l5 ccap1l4 ccap1l3 ccap1l2 ccap1l1 ccap1l0 ccap2l ech pca comp a re c a pt u re mod u le 2 l ccap2l7 ccap2l6 ccap2l5 ccap2l4 ccap2l3 ccap2l2 ccap2l1 ccap2l0 ccap3l edh pca comp a re c a pt u re mod u le 3 l ccap3l7 ccap3l6 ccap3l5 ccap3l4 ccap3l3 ccap3l2 ccap3l1 ccap3l0 ccap4l eeh pca comp a re c a pt u re mod u le 4 l ccap4l7 ccap4l6 ccap4l5 ccap4l4 ccap4l3 ccap4l2 ccap4l1 ccap4l0 table 4-15. pca s frs (contin u ed) mnemo -nicaddname 76543210
30 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary
31 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 5. enhanced cpu the at 8 9lp51rb2/rc2/ic2 u ses a n enh a nced 8 051 cpu th a t r u ns a t 6 to 12 times the speed of st a nd a rd 8 051 devices (or 3 to 6 times the speed of x2 8 051 devices). the incre a se in perfor- m a nce is d u e to two f a ctors. first, the cpu fetches one instr u ction byte from the code memory every clock cycle. s econd, the cpu u ses a simple two-st a ge pipeline to fetch a nd exec u te instr u ctions in p a r a llel. this b a sic pipelining concept a llows the cpu to obt a in u p to 1mip s per mhz. the at 8 9lp51rb2/rc2/ic2 a lso h a s a comp a tibility mode th a t preserves the 12-clock m a chine cycle of st a nd a rd 8 051s like the at 8 9c51rb2/rc2/ic2. 5.1 fast mode f a st ( s ingle-cycle) mode m u st be en a bled by cle a ring the comp a tibility user f u se. ( s ee ?user config u r a tion f u ses? on p a ge 1 88 .) in this mode one instr u ction byte is fetched every system clock cycle. the 8 051 instr u ction set a llows for instr u ctions of v a ri a ble length from 1 to 3 bytes. in a single-clock-per-byte-fetch system this me a ns e a ch instr u ction t a kes a t le a st a s m a ny clocks a s it h a s bytes to exec u te. the m a jority of instr u ctions in the at 8 9lp51rb2/rc2/ic2 fol- low this r u le: the instr u ction exec u tion time in system clock cycles eq ua ls the n u mber of bytes per instr u ction, with a few exceptions. br a nches a nd c a lls req u ire a n a ddition a l cycle to com- p u te the t a rget a ddress a nd some other complex instr u ctions req u ire m u ltiple cycles. s ee ?instr u ction s et su mm a ry? on p a ge 173. for more det a iled inform a tion on individ ua l instr u ctions. ex a mple of f a st mode instr u ctions a re shown in fig u re 5-1 . note th a t f a st mode instr u ctions t a ke three times a s long to exec u te if they a re fetched from extern a l progr a m memory. figure 5-1. instr u ction exec u tion s eq u ences in f a st mode read next opcode (a) 1- b yte, 1-cycle in s truction, e.g. inc a s1 (b) 2- b yte, 2-cycle in s truction, e.g. add a, #data s1 s2 read next opcode read operand (c) 1- b yte, 2-cycle in s truction, e.g. inc dptr s1 s2 read next opcode (d) movx (1- b yte, 4-cycle) s1 s2 s 3 s4 addr data access external memory clk read next opcode
32 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 5.2 compatibility mode comp a tibility (12-clock) mode is en a bled by def au lt from the f a ctory or by setting the comp a ti- bility user f u se. in comp a tibility mode instr u ction bytes a re fetched every three system clock cycles a nd the cpu oper a tes with 6-st a te m a chine cycles a nd a divide-by-2 system clock for 12 oscill a tor periods per m a chine cycle. s t a nd a rd instr u ctions exec u te in1, 2 or 4 m a chine cycles. instr u ction timing in this mode is comp a tible with st a nd a rd 8 051s s u ch a s the at 8 9c51rb2/rc2/ic2. in comp a tibility mode there is no difference in timing between instr u c- tions exec u ted from intern a l vers u s extern a l progr a m memory. comp a tibility mode c a n be u sed to preserve the exec u tion profiles of leg a cy a pplic a tions. for a s u mm a ry of differences between f a st a nd comp a tibility modes see t a ble 2-3 on p a ge 12 . ex a mples of comp a tibility mode instr u ctions a re shown in fig u re 5-2 . figure 5-2. instr u ction exec u tion s eq u ences in comp a tibility mode 5.3 multiply?accumulate unit (mac) the at 8 9lp51rb2/rc2/ic2 incl u des a m u ltiply a nd a cc u m u l a te (mac) u nit th a t c a n signifi- c a ntly speed u p m a ny m a them a tic a l oper a tions req u ired for digit a l sign a l processing. the mac u nit incl u des a 16-by-16 bit m u ltiplier a nd a 40-bit a dder th a t c a n perform integer or fr a ction a l m u ltiply- a cc u m u l a te oper a tions on signed 16-bit inp u t v a l u es. the mac u nit a lso incl u des a 1-bit a rithmetic shifter th a t will left or right shift t he contents of the 40-bit mac a cc u m u l a tor register (m). s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 clk c l k ale a l e read opcode r e a d o p c o d e (a) 1- b yte, 1-cycle in s truction, e.g., inc a a (b) 2- b yte, 1-cycle in s truction, e.g., add a, #data ( b ) 2 - b y t e , 1 - c y c l e i n s t r u c t i o n , e . g . , a d d a , # d a t a (c) 1- b yte, 2-cycle in s truction, e.g., inc dptr ( c ) 1 - b y t e , 2 - c y c l e i n s t r u c t i o n , e . g . , i n c d p t r (d) movx (1- b yte, 2-cycle) ( d ) m o v x ( 1 - b y t e , 2 - c y c l e ) read next r e a d n e x t opcode o p c o d e (discard) ( d i s c a r d ) read next opcode again r e a d n e x t o p c o d e a g a i n read opcode r e a d o p c o d e read 2nd r e a d 2 n d byte b y t e read next opcode r e a d n e x t o p c o d e read opcode r e a d o p c o d e read next r e a d n e x t opcode again o p c o d e a g a i n read r e a d opcode o p c o d e (movx) ( m o v x ) no n o ale a l e read next r e a d n e x t opcode (discard) o p c o d e ( d i s c a r d ) read next r e a d n e x t opcode o p c o d e again a g a i n no n o fetch f e t c h da d a t a access external memor a c c e s s e x t e r n a l m e m o r y addr a d d r no n o fetch f e t c h read next r e a d n e x t opcode (discard) o p c o d e ( d i s c a r d )
33 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary a block di a gr a m of the mac u nit is shown in fig u re 5-3 . the 16-bit signed oper a nds a re pro- vided by the register p a irs (ax,acc) a nd (bx,b) where ax (e1h) a nd bx (f7h) hold the higher order bytes. the 16-by-16 bit m u ltiplic a tion is comp u ted thro u gh p a rti a l prod u cts u sing the at 8 9lp51rb2/rc2/ic2?s 8 -bit m u ltiplier. the 32-bit signed prod u ct is a dded to the 40-bit m a cc u m u l a tor register. the mac oper a tion is s u mm a rized a s follows: all comp u t a tion is done in signed two?s complement form. figure 5-3. m u ltiply?acc u m u l a te unit the mac oper a tion is performed by exec u ting the mac ab (a5 a4h) extended instr u ction. this two-byte instr u ction req u ires nine clock cycles to complete a s the m u ltiply is done in a seq u enti a l m a nner u sing p a rti a l prod u cts. the oper a nd registers a re not modified by the instr u ction a nd the res u lt is stored in the 40-bit m register. mac ab a lso u pd a tes the c a nd ov fl a gs in p s w. c rep- resents the sign of the mac res u lt a nd ov is the two?s complement overflow. note th a t mac ab will not cle a r ov if it w a s previo u sly set to one. three a ddition a l extended instr u ctions oper a te directly on the m register. clr m (a5 e4h) cle a rs the entire 40-bit register in two clock cycles. l s l m (a5 23h) a nd a s r (a5 03h) shift m one bit to the left a nd right respectively. right shifts a re done a rithmetic a lly, i.e. the sign is preserved. the 40-bit m register is a ccessible 16-bits a t a time thro u gh a sliding window a s shown in fig u re 5-4 . the mrw 1-0 bits in d s pr ( t a ble 5-1 ) select which 16-bit segment is c u rrently a ccessible thro u gh the macl a nd mach a ddresses. for norm a l fixed point oper a tions the window c a n be fixed to the r a nk of interest. for ex a mple, m u ltiplying two 1.15 form a t n u mbers pl a ces a 2.30 for- m a t res u lt in the m register. if mrw is set to 10b, a 1.15 v a l u e is obt a ined a fter performing a single l s l m. mac ab: m m ax acc {, } bx b {,} + 3 m4 m2 m1 m0 acc ax bx b 16 x 16- b it signed mult 40- b it add shifter mach macl psw mrw smla smlb
34 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 5-4. m register with s liding window as a conseq u ence of the mac u nit, the st a nd a rd 8 x 8 mul ab instr u ction c a n s u pport signed m u ltiplic a tion. the s mla a nd s mlb bits in d s pr control the m u ltiplier?s interpret a tion of the acc a nd b registers, a llowing a ny combin a tion of signed a nd u nsigned oper a nd m u ltiplic a tion. these bits h a ve no effect on the mac oper a tion which a lw a ys m u ltiplies signed-by-signed. m 2 3 ? 16 15 ? 8 7 ? 0 3 1 ? 24 3 9 ? 3 2 byte 4 byte 3 byte 2 byte 1 byte 0 mach macl mach macl mach macl mach macl mrw 1-0 = 00b mrw 1-0 = 01b mrw 1-0 = 10b mrw 1-0 = 11b table 5-1. d s pr ? digit a l s ign a l processing config u r a tion register d s pr = e2h reset v a l u e = 0000 0000b not bit address a ble mrw1 mrw0 s mlb s mla cbe1 cbe0 mvcd dprb bit76543210 symbol function mrw 1-0 m register window. s elects which p a ir of bytes from the 5-byte m register is a ccessible thro u gh mach (e5h) a nd macl (e4h) a s shown in fig u re 5-4 . for ex a mple, mrw = 10b for norm a l 16-bit fixed-point oper a tions where the lowest order portion of the fr a ction a l res u lt is disc a rded. s mlb s igned m u ltiply oper a nd b. when s mlb = 0, the mul ab instr u ction tre a ts the contents of b a s a n u nsigned v a l u e. when s mlb = 1, the mul ab instr u ction interprets the contents of b a s a signed two?s complement v a l u e. s mlb does not a ffect the mac oper a tion. s mla s igned m u ltiply oper a nd a. when s mla = 0, the mul ab instr u ction tre a ts the contents of acc a s a n u nsigned v a l u e. when s mla = 1, the mul ab instr u ction interprets the contents of acc a s a signed two?s complement v a l u e. s mla does not a ffect the mac oper a tion. cbe1 dptr1 circ u l a r b u ffer en a ble. s et cbe1 = 1 to config u re dptr1 for circ u l a r a ddressing over the two circ u l a r b u ffer a ddress r a nges. cle a r cbe1 for norm a l dptr oper a tion. cbe0 dptr0 circ u l a r b u ffer en a ble. s et cbe0 = 1 to config u re dptr0 for circ u l a r a ddressing over the two circ u l a r b u ffer a ddress r a nges. cle a r cbe0 for norm a l dptr oper a tion. mvcd movc index dis a ble. when mvcd = 0, the movc a, @a+dptr instr u ction f u nctions norm a lly with indexed a ddressing. s etting mvcd = 1 dis a bles the indexed a ddressing mode s u ch th a t movc a, @a+dptr f u nctions a s movc a, @dptr. dprb dptr1 redirect to b. dprb selects the so u rce/destin a tion register for movc/movx instr u ctions th a t reference dptr1. when dprb = 0, acc is the so u rce/destin a tion. when dprb = 1, b is the so u rce/destin a tion. dprb does not ch a nge the index register for movc instr u ctions.
35 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 5.4 enhanced dual data pointers the at 8 9lp51rb2/rc2/ic2 provides two 16-bit d a t a pointers: dptr0 a nd dptr1. the d a t a pointers a re u sed by sever a l instr u ctions to a ccess the progr a m or d a t a memories. the a u xili a ry 1 register (auxr1) a nd d a t a pointer config u r a tion register (dpcf) control oper a tion of the d ua l d a t a pointers (see t a ble 5-6 on p a ge 37 a nd t a ble 5-7 on p a ge 37 ). the dp s bit in auxr1 selects which d a t a pointer is c u rrently referenced by instr u ctions incl u ding the dptr oper a nd. e a ch d a t a pointer m a y a lso be a ccessed a t a p a ir of s fr a ddresses th a t a lso depend on the dp s v a l u e. the d a t a pointer referenced by dp s is loc a ted a t the register p a ir dpl a nd dph ( 8 2h a n 8 3h), a nd the a ltern a te d a t a pointer not referenced by dp s is loc a ted a t the regis- ter p a ir dplb a nd dphb (d4h a nd d5h). when dp s is toggled, the two d a t a pointers a lso sw a p which s fr p a ir will a ccess them a s shown in t a ble 5-2 . the at 8 9lp51rb2/rc2/ic2 provides two methods for f a st context switching of the d a t a pointers: ? bit 2 of auxr1 is h a rd-wired a s a logic 0. the dp s bit m a y be toggled (to switch d a t a pointers) simply by incrementing the auxr1 register, witho u t a ltering other bits in the register u nintention a lly. this is the preferred method when only a single d a t a pointer will be u sed a t one time. ex: inc auxr1 ; toggle dps ?in some c a ses, both d a t a pointers m u st be u sed sim u lt a neo u sly. to prevent freq u ent toggling of dp s , the at 8 9lp51rb2/rc2/ic2 s u pports a prefix not a tion for selecting the opposite d a t a pointer per instr u ction. all dptr instr u ctions, with the exception of jmp @a+dptr, when prefixed with a n 0a5h opcode will u se the inverse v a l u e of dp s (dp s ) to select the d a t a pointer. s ome a ssemblers m a y s u pport this oper a tion by u sing the /dptr oper a nd. for ex a mple, the following code performs a block copy within edata: mov auxr1, #00h ; dps = 0 mov dptr, #src ; load source address to dptr0 mov /dptr, #dst ; load destination address to dptr1 mov r7, #blksize ; number of bytes to copy copy: movx a, @dptr ; read source (dptr0) inc dptr ; next src (dptr0+1) movx @/dptr, a ; write destination (dptr1) inc /dptr ; next dst (dptr1+1) djnz r7, copy for a ssemblers th a t do not s u pport this not a tion, the 0a5h prefix m u st be decl a red in-line: ex: db 0a5h inc dptr ; equivalent to inc /dptr table 5-2. d a t a pointer register access sfr dps = 0 dps = 1 dpl ( 8 2h) dp0l dp1l dph ( 8 3h) dp0h dp1h dplb (d4h) dp1l dp0l dphb (d5h) dp1h dp0h
36 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary a s u mm a ry of d a t a pointer instr u ctions with f a st context switching is listed in t a ble 5-3 . 5.4.1 data pointer update the d ua l d a t a pointers on the at 8 9lp51rb2/rc2/ic2 incl u de two fe a t u res th a t control how the d a t a pointers a re u pd a ted. the d a t a pointer decrement bits, dpd1 a nd dpd0 in auxr1, config u re the inc dptr instr u ction to a ct a s dec dptr. the res u lting oper a tion will depend on dp s a s shown in t a ble 5-4 . these bits a lso control the direction of au to- u pd a tes d u ring movc a nd movx. the d a t a pointer u pd a te bits, dpu1 a nd dpu0, a llow movx @dptr a nd movc @dptr instr u ctions to u pd a te the selected d a t a pointer au tom a tic a lly in a post-increment or post-decre- ment f a shion. the direction of u pd a te depends on the dpd1 a nd dpd0 bits a s shown in t a ble 5-5 . these bits c a n be u sed to m a ke block copy ro u tines more efficient. note th a t dpcf sho u ld be cle a red to zero, dis a bling these modes, before a ny c a lls a re m a de to the fl a sh api.c a re m u st a lso be t a ken when interr u pt ro u tines u se d a t a pointers to ens u re th a t correct oper a tion is s a ved/restored correctly. table 5-3. d a t a pointer instr u ctions instruction operation dps = 0 dps = 1 jmp @a+dptr jmp @a+dptr0 jmp @a+dptr1 mov dptr, #d a t a 16 mov dptr0, #d a t a 16 mov dptr1, #d a t a 16 mov /dptr, #d a t a 16 mov dptr1, #d a t a 16 mov dptr0, #d a t a 16 inc dptr inc dptr0 inc dptr1 inc /dptr inc dptr1 inc dptr0 movc a,@a+dptr movc a,@a+dptr0 movc a,@a+dptr1 movc a,@a+/dptr movc a,@a+dptr1 movc a,@a+dptr0 movx a,@dptr movx a,@dptr0 movx a,@dptr1 movx a,@/dptr movx a,@dptr1 movx a,@dptr0 movx @dptr, a movx @dptr0, a movx @dptr1, a movx @/dptr, a movx @dptr1, a movx @dptr0, a table 5-4. d a t a pointer decrement beh a vior dpd1 dpd0 equivalent operation for inc dptr and inc /dptr dps = 0 dps = 1 inc dptr inc /dptr inc dptr inc /dptr 0 0 inc dptr0 inc dptr1 inc dptr1 inc dptr0 0 1 dec dptr0 inc dptr1 inc dptr1 dec dptr0 1 0 inc dptr0 dec dptr1 dec dptr1 inc dptr0 1 1 dec dptr0 dec dptr1 dec dptr1 dec dptr0
37 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 5-5. d a t a pointer a u to-upd a te dpd1 dpd0 update operation for movx and movc (dpu1 = 1 & dpu0 = 1) dps = 0 dps = 1 dptr /dptr dptr /dptr 0 0 dptr0++ dptr1++ dptr1++ dptr0++ 0 1 dptr0-- dptr1++ dptr1++ dptr0-- 1 0 dptr0++ dptr1-- dptr1-- dptr0++ 1 1 dptr0-- dptr1-- dptr1-- dptr0-- table 5-6. auxr1 ? a u xili a ry register 1 auxr1 = a2h reset v a l u e = xxx0 00x0b not bit address a ble ? ? enboot x s tk gf3 0 ? dp s bit76543210 symbol function enboot s et enboot = 1 to m a p the boot rom in the r a nge f 8 00h?ffffh. this is req u ired to r u n the bootlo a der or a ccess the fl a sh api. when enboot = 0 the boot rom is not a ccessible a nd norm a l progr a m memory is m a pped to this r a nge. the def au lt v a l u e is set by the bootlo a der j u mp bit. s ee s ection 24.2 on p a ge 1 88 . x s tk extended s t a ck en a ble. when x s tk = 0 the st a ck resides in idata a nd is limited to 256 bytes. s et x s tk = 1 to pl a ce the st a ck in edata for u p to 2k bytes of extended st a ck sp a ce. all pu s h, pop, call a nd ret instr u ctions will inc u r a one or two cycle pen a lty when a ccessing the extended st a ck. gf3 this bit is a gener a l p u rpose u ser fl a g. dp s d a t a pointer s elect. dp s selects the a ctive d a t a pointer for instr u ctions th a t reference dptr. when dp s = 0, dptr will t a rget dptr0 a nd /dptr will t a rget dptr1. when dp s = 1, dptr will t a rget dptr1 a nd /dptr will t a rget dptr0. table 5-7. dpcf ? d a t a pointer config u r a tion register dpcf = a1h reset v a l u e = 0000 00x0b not bit address a ble dpu1 dpu0 dpd1 dpd0 ? ? ? ? bit76543210 symbol function dpu1 d a t a pointer 1 upd a te. when set, movx @dptr a nd movc @dptr instr u ctions th a t u se dptr1 will a lso u pd a te dptr1 b a sed on dpd1. if dpd1 = 0 the oper a tion is post-increment a nd if dpd1 = 1 the oper a tion is post-decrement. when dpu1 = 0, dptr1 is not u pd a ted. dpu0 d a t a pointer 0 upd a te. when set, movx @dptr a nd movc @dptr instr u ctions th a t u se dptr0 will a lso u pd a te dptr0 b a sed on dpd0. if dpd0 = 0 the oper a tion is post-increment a nd if dpd0 = 1 the oper a tion is post-decrement. when dpu0 = 0, dptr0 is not u pd a ted. dpd1 d a t a pointer 1 decrement. when set, inc dptr instr u ctions t a rgeted to dptr1 will decrement dptr1. when cle a red, inc dptr instr u ctions will increment dptr1. dpd1 a lso determines the direction of au to- u pd a te for dptr1 when dpu1 = 1. dpd0 d a t a pointer 0 decrement. when set, inc dptr instr u ctions t a rgeted to dptr0 will decrement dptr0. when cle a red, inc dptr instr u ctions will increment dptr0. dpd0 a lso determines the direction of au to- u pd a te for dptr0 when dpu0 = 1.
38 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 5.4.2 data pointer operating modes the d ua l d a t a pointers on the at 8 9lp51rb2/rc2/ic2 incl u de three a ddition a l oper a ting modes th a t a ffect d a t a pointer b a sed instr u ctions. these modes a re controlled by bits in d s pr. note th a t these bits in d s pr sho u ld be cle a red to zero, dis a bling these modes, before a ny c a lls a re m a de to the fl a sh api.c a re m u st a lso be t a ken when interr u pt ro u tines u se d a t a pointers to ens u re th a t correct oper a tion is s a ved/restored correctly. 5.4.2.1 dptr redirect the d a t a pointer redirect to b bit, dprb (d s pr.0), a llows movx a nd movc instr u ctions to u se the b register a s the d a t a so u rce/destin a tion when the instr u ction references dptr1 a s shown in t a ble 5- 8 a nd t a ble 5-9 . dprb c a n improve the efficiency of ro u tines th a t m u st fetch m u ltiple oper a nds from different ram loc a tions. 5.4.2.2 index disable the movc index dis a ble bit, mvcd (d s pr.1), dis a bles the indexed a ddressing mode of the movc a, @a+dptr instr u ction. when mvcd = 1, the movc instr u ction f u nctions a s movc a, @dptr with no indexing a s shown in t a ble 5-9 . mvcd c a n improve the efficiency of ro u tines th a t m u st fetch m u ltiple oper a nds from progr a m memory. dprb c a n ch a nge the movc destin a tion register from acc to b, b u t h a s no effect on the movc index register. table 5-8. movx @dptr oper a ting modes dprb dps equivalent operation for movx movx a, @dptr movx @dptr, a dptr /dptr dptr /dptr 00 movx a, @dptr0 movx a, @dptr1 movx @dptr0, a movx @dptr1, a 01 movx a, @dptr1 movx a, @dptr0 movx @dptr1, a movx @dptr0, a 10 movx a, @dptr0 movx b, @dptr1 movx @dptr0, a movx @dptr1, b 11 movx b, @dptr1 movx a, @dptr0 movx @dptr1, b movx @dptr0, a table 5-9. movc @dptr oper a ting modes mvcd dprb equivalent operation for movc a, @a+dptr dps = 0 dps = 1 dptr /dptr dptr /dptr 00 movc a, @a+dptr0 movc a, @a+dptr1 movc a, @a+dptr1 movc a, @a+dptr0 01 movc a, @a+dptr0 movc b, @a+dptr1 movc b, @a+dptr1 movc a, @a+dptr0 10 movc a, @dptr0 movc a, @dptr1 movc a, @dptr1 movc a, @dptr0 11 movc a, @dptr0 movc b, @dptr1 movc b, @dptr1 movc a, @dptr0
39 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 5.4.2.3 circular buffers the cbe0 a nd cbe1 bits in d s pr c a n config u re dptr0 a nd dptr1, respectively, to oper a te in circ u l a r b u ffer mode. the at 8 9lp51rb2/rc2/ic2 m a ps circ u l a r b u ffers into two identic a lly sized regions of edata/xdata. these b u ffers c a n speed u p convol u tion comp u t a tions s u ch a s fir a nd iar digit a l filters. the le ngth of the b u ffers a re set by the v a l u e of the fird (e3h) regis- ter for u p to 256 entries. b u ffer a is m a pped from 0000h to fird a nd b u ffer b is m a pped from 0100h to 100h+fird a s shown in fig u re 5-5 . both d a t a pointers m a y oper a te in either b u ffer. when circ u l a r b u ffer mode is en a bled, u pd a tes to a d a t a pointer referencing the b u ffer region will follow circ u l a r a ddressing r u les. if the d a t a pointer is eq ua l to fird or 100h+fird a ny incre- ment will c au se it to overflow to 0000h or 0100h respectively. if the d a t a pointer is eq ua l to 0000h or 0100h a ny decrement will c au se it to u nderflow to fird or 100h+fird respectively. in this mode, u pd a tes c a n be either a n explicit inc dptr or a n au tom a tic u pd a te u sing dpu n where the dpd n bits control the direction. the d a t a pointer will increment or decrement norm a lly a t a ny other a ddresses. therefore, when circ u l a r a ddressing is in u se, the d a t a pointers c a n still oper a te a s reg u l a r pointers in the fird+1 to 00ffh a nd gre a ter th a n 100h+fird r a nges. figure 5-5. circ u l a r b u ffer mode 5.5 instruction set extensions t a ble 5-10 lists the a dditions to the 8 051 instr u ction set th a t a re s u pported by the at 8 9lp51rb2/rc2/ic2. for more inform a tion on the instr u ction set see s ection 22. ?instr u ction s et su mm a ry? on p a ge 173 . for det a iled descriptions of the extended instr u ctions see s ection 22.1 ?instr u ction s et extensions? on p a ge 177 . 0000h dptr 0100h fird 100h + fird dptr dpdn = 0 dpdn = 1 dpdn = 0 dpdn = 1 a b table 5-10. at 8 9lp51rb2/rc2/ic2 extended instr u ctions opcode mnemonic description bytes cycles a5 00 break s oftw a re bre a kpoint 2 2 a5 03 a s r m arithmetic shift right of m register 2 2 a5 23 l s l m logic a l shift left of m register 2 2 a5 73 jmp @a+pc indirect j u mp rel a tive to pc 2 3 a5 90 mov /dptr, #d a t a 16 move 16-bit const a nt to a ltern a te d a t a pointer 44 a5 93 movc a, @a+/dptr move code loc a tion to acc rel a tive to a ltern a te d a t a pointer 24 a5 a3 inc /dptr increment a ltern a te d a t a pointer 2 3
40 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ? the /dptr instr u ctions provide s u pport for the d ua l d a t a pointer fe a t u res described a bove ( s ee s ection 5.4 ). ?the a s r m, l s l m, clr m a nd mac ab instr u ctions a re p a rt of the m u ltiply-acc u m u l a te unit ( s ee s ection 5.3 ). ? the jmp @a+pc instr u ction s u pports loc a lized j u mp t a bles witho u t u sing a d a t a pointer. ?the cjne a, @r i , rel instr u ctions a llow comp a res of a rr a y v a l u es with non-const a nt v a l u es. ? the break instr u ction is u sed by the on-chip deb u g system. s ee s ection 23. on p a ge 1 8 3 . ? s ome third p a rty a ssemblers/compilers do not s u pport these instr u ctions. in order to u se them yo u m a y need to write a ssembly f u nctions th a t em u l a te the instr u ction by decl a ring the opcodes inline a s shown in t a ble 5-11 . a5 a4 mac ab m u ltiply a nd a cc u m u l a te 2 9 a5 b6 cjne a, @r0, rel comp a re acc to indirect ram a nd j u mp if not eq ua l 34 a5 b7 cjne a, @r1, rel comp a re acc to indirect ram a nd j u mp if not eq ua l 34 a5 e0 movx a, @/dptr move extern a l to acc; 16-bit a ddress in a ltern a te d a t a pointer 23/5 a5 e4 clr m cle a r m register 2 2 a5 f0 movx @/dptr, a move acc to extern a l; 16-bit a ddress in a ltern a te d a t a pointer 23/5 table 5-11. extended instr u ction assembly em u l a tions opcode mnemonic emulation a5 00 break db a5h, 00h a5 03 a s r m db a5h, 03h or db a5h followed by rr a a5 23 l s l m db a5h, 23h or db a5h followed by rl a a5 73 jmp @a+pc db a5h, 73h or db a5h followed by jmp @a+dptr a5 90 mov /dptr, #d a t a 16 db a5h followed by mov dptr, #d a t a 16 a5 93 movc a, @a+/dptr db a5h, 93h or db a5h followed by movc a, @a+dptr a5 a3 inc /dptr db a5h, a3h or db a5h followed by inc dptr a5 a4 mac ab db a5h, a4h or db a5h followed by mul ab a5 b6 cjne a, @r0, rel db a5h, b6 h, (label-$-3) where label is the j u mp t a rget a5 b7 cjne a, @r1, rel db a5h, b7 h, (label-$-3) where label is the j u mp t a rget a5 e0 movx a, @/dptr db a5h, e0h or db a5h followed by movx a, @dptr a5 e4 clr m db e4h, e0h or db a5h followed by clr a a5 f0 movx @/dptr, a db a5h, f0h or db a5h followed by movx @dptr, a table 5-10. at 8 9lp51rb2/rc2/ic2 extended instr u ctions opcode mnemonic description bytes cycles
41 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6. system clock the at 8 9lp51rb2/rc2 h a s a single system clock th a t is gener a ted directly from one of three select a ble clock so u rces: on-chip cryst a l oscill a tor a in high or low power oper a tion, extern a l clock so u rce on xtal1a, a nd the intern a l 8 mhz rc oscill a tor. a di a gr a m of the clock s u bsys- tem is shown in fig u re 6-1 . the clock so u rce is selected by the clock s o u rce a user f u ses a s shown in t a ble 6-1 ( s ee ?user config u r a tion f u ses? on p a ge 1 88 ). in a ddition to this system clock, the at 8 9lp51ic2 device a dds a second system clock so u rce th a t is select a ble from on- chip low freq u ency cryst a l oscill a tor b in, extern a l clock so u rce on xtal1b, a nd the intern a l 8 mhz rc oscill a tor. a di a gr a m of this clock s u bsystem is shown in fig u re 6-2 . clock so u rce b is selected by the clock s o u rce b user f u ses a s shown in t a ble 6-2 . the choice of clock so u rce a lso a ffects the st a rt- u p time a fter a por, bod or power-down event ( s ee ?reset? on p a ge 51 or ?power-down mode? on p a ge 56 ). the at 8 9lp51rb2/rc2/ic2 incl u des a x1/x2 fe a t u re for comp a tibility with at 8 9c51rb2/rc2/ic2. this fe a t u re determines if the oscill a tor so u rce is divided by two or not to gener a te the system clock. the 8 -bit system clock divider m a y be u sed to presc a le the system clock to red u ce the oper a ting freq u ency. in a ddition a 4-bit presc a ler is a v a il a ble to ch a nge the clocks of the peripher a ls. figure 6-1. at 8 9lp51rb2/rc2 clock su bsystem di a gr a m figure 6-2. at 8 9lp51ic2 clock su bsystem di a gr a m xtal1a xtal2a system clock (clk sys ) internal 8.0 mhz osc 0 1 2 3 8-bit clock divider clk irc clk ext clk xtal clock fuse a 4-bit prescaler tps 3 -0 timer 0 timer 1 timer 2 pca watchdog 2 0 1 x2 (ckcon0.0) ckrl 0 1 ckrl != ffh osca xtal1a xtal2a system clock (clk sys ) internal 8.0 mhz osc 0 1 2 3 8-bit clock divider clk irc clk exta clk xtala clock fuse a 4-bit prescaler tps 3 -0 timer 0 timer 1 timer 2 pca watchdog 2 0 1 x2 (ckcon0.0) ckrl 0 1 ckrl != ffh osca xtal1b xtal2b 0 1 2 3 clk ir c clk extb clk xtalb clock fuse b oscb o s caen (oscon.0) o s cben (oscon.1) 0 1 cks (cksel.0) 128 timer 0 su b clock timer 2 (extb or xtalb only via t2 )
42 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.1 crystal oscillator a when en a bled, intern a l inverting oscill a tor a mplifier a is connected between xtal1a a nd xtal2a for connection to a n extern a l q ua rtz cryst a l or cer a mic reson a tor. the oscill a tor m a y oper a te in either high-speed or low-power mode. low-power mode is intended for cryst a ls of 12 mhz or less a nd cons u mes less power th a n the higher speed mode. the config u r a tion a s shown in fig u re 6-3 a pplies for both high a nd low power oscill a tors. note th a t in some c a ses, extern a l c a p a citors c1 a nd c2 m a y be red u ced d u e to the on-chip c a p a cit a nce of the xtal1a a nd xtal2a inp u ts ( a pproxim a tely 10 pf e a ch). when u sing the cryst a l oscill a tor, p4.6 a nd p4.7 will h a ve their inp u ts a nd o u tp u ts dis a bled. also, xtal2a in cryst a l oscill a tor mode sho u ld not be u sed to directly drive a bo a rd-level clock witho u t a b u ffer. an option a l 5 m on-chip resistor c a n be connected between xtal1a a nd gnd. this resistor c a n improve the st a rt u p ch a r a cteristics of the oscill a tor especi a lly a t higher freq u encies. the resistor c a n be en a bled/dis a bled with the r1 user f u se ( s ee ?user config u r a tion f u ses? on p a ge 1 88 . ) figure 6-3. cryst a l oscill a tor a connections note: 1. c1, c2 = 5?15 pf for cryst a ls = 5?15 pf for cer a mic reson a tors table 6-1. clock s o u rce a s ettings clock source a fuse 1 clock source a fuse 0 selected clock source 1 1 high s peed cryst a l oscill a tor a (f > 12 mhz) 1 0 low power cryst a l oscill a tor a (f 12 mhz) 01extern a l clock on xtal1a 0 0 intern a l 8 .0 mhz rc oscill a tor table 6-2. clock s o u rce b s ettings (at 8 9lp51ic2 only) clock source b fuse 1 clock source b fuse 0 selected clock source 1 ? low freq u ency cryst a l oscill a tor b (32 khz) 01extern a l clock on xtal1b 0 0 intern a l 8 .0 mhz rc oscill a tor ~10 pf ~10 pf c2 c1 r1 ~5 m
43 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.2 external clock source a the extern a l clock option dis a bles the oscill a tor a mplifier a nd a llows xtal1a to be driven directly by a n extern a l clock so u rce a s shown in fig u re 6-4 . xtal2a m a y be left u nconnected, u sed a s gener a l p u rpose i/o p4.7, or config u red to o u tp u t a divided version of the system clock. figure 6-4. extern a l clock a drive config u r a tion 6.3 internal rc oscillator the at 8 9lp51rb2/rc2/ic2 h a s a n intern a l rc oscill a tor t u ned to 8 .0 mhz 2.5%. when en a bled a s clock so u rce a, xtal1a a nd xtal2a m a y be u sed a s p4.6 a nd p4.7 respectively. for at 8 9lp51ic2 the intern a l oscill a tor c a n a lso be selected for clock so u rce b, freeing u p xtal1b a nd xtal2b to a ct a s p1.0 a nd p4.2 respectively. the freq u ency of the oscill a tor m a y be a dj u sted within limits by ch a nging the rc c a libr a tion byte stored a t byte 3 8 4 of the user s ig- n a t u re arr a y. this loc a tion m a y be u pd a ted u sing the iap interf a ce or by a n extern a l device progr a mmer (user s ign a t u re loc a tion 01 8 0h). s ee s ection 24.1.2 ?atmel s ign a t u re arr a y? on p a ge 1 88 . a copy of the f a ctory c a libr a tion byte is stored a t byte 8 of the atmel s ign a t u re arr a y (000 8 h in s ig sp a ce). 6.4 crystal oscill ator b (at89lp51ic2) at 8 9lp51ic2 incl u des a second cryst a l oscill a tor for low-freq u ency ( ~ 32 khz) oper a tion. when en a bled, intern a l inverting oscill a tor a mplifier b is connected between xtal1b a nd xtal2b for connection to a n extern a l q ua rtz cryst a l or cer a mic reson a tor a s shown in fig u re 6-5 . note th a t in some c a ses, extern a l c a p a citors c1 a nd c2 m a y be red u ced d u e to the on-chip c a p a cit a nce of the xtal1b a nd xtal2b inp u ts ( a pproxim a tely 10 pf e a ch). an on-chip series resist a nce is incl u ded between the a mplifier a nd the xtal2b p a d to limit the drive level. in most c a ses a n extern a l series resistor is not req u ired. when u sing the cryst a l oscill a tor, p1.0 a nd p4.2 will h a ve their inp u ts a nd o u tp u ts dis a bled. also, xtal2b in cryst a l oscill a tor mode sho u ld not be u sed to directly drive a bo a rd-level clock witho u t a b u ffer. ple a se note th a t the low-freq u ency oscill a tor m a y h a ve a very long settling time. the system m u st ens u re th a t the oscill a tor h a s s u fficient time to st a bilize before the device is a llowed to oper a te from this clock so u rce. xt al2a (p4.7) xt al1a (p4.6) gnd nc gpio external oscilla t or signal
44 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 6-5. cryst a l oscill a tor b connections note: 1. c1, c2 = 10?20 pf for cryst a ls = 10?20 pf for cer a mic reson a tors 6.5 external clock source b (at89lp51ic2) the extern a l clock option of at 8 9lp51ic2 dis a bles the oscill a tor a mplifier b a nd a llows xtal1b to be driven directly by a n extern a l clock so u rce a s shown in fig u re 6-6 . xtal2b m a y be left u nconnected or u sed a s gener a l p u rpose i/o p4.2. figure 6-6. extern a l clock a drive config u r a tion 6.6 dual oscillator support (at89lp51ic2) the at 8 9lp51ic2 h a s the a bility to switch between two different select a ble system clock so u rces u nder softw a re control a s shown in fig u re 6-2 on p a ge 41 . ?o s ca c a n be a high freq u ency cryst a l, extern a l clock or the intern a l 8 mhz oscill a tor ?o s cb c a n be a low freq u ency cryst a l, extern a l clock or the intern a l 8 mhz oscill a tor s ever a l oper a ting modes a re a v a il a ble a nd progr a mm a ble by softw a re: ? s witch system clock so u rce from o s ca to o s cb a nd vice-vers a ?power down o s ca or o s cb to red u ce cons u mption ?boot from a f a st responding, less a cc u r a te oscill a tor a nd switch l a ter to a more a cc u r a te b u t slow to st a bilize oscill a tor. s election of which oscill a tor drives the system cloc k is controlled by the ck s bit in ck s el. in order to switch to a different oscill a tor, th a t oscill a tor m u st be en a bled with the oscaen or osc- ~10 pf ~10 pf c2 rd c1 xtal2b xtal1b xt al2b (p4.2) xt al1b (p1.0) gnd nc gpio external oscilla t or signal
45 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ben bits in o s ccon. the oscill a tor selection a t reset is controlled by the oscill a tor s elect u ser f u se ( s ee s ection 24.2 on p a ge 1 88 ). this f u se is a lso sh a dowed in the o s c bit of the boot- lo a der h a rdw a re s ec u rity byte. the f u se sets the ck s , oscaen a nd oscben bits a s shown in t a ble 6-3 . 6.6.1 normal operation only a single oscill a tor so u rce c a n drive the system clock a t a ny one time. under norm a l condi- tions it is a lw a ys possible to dyn a mic a lly switch from o s ca to o s cb or vice-vers a by ch a nging the ck s bit. the proced u re is a s follows: 1. en a ble the desired oscill a tor by setting the oscaen or oscben bits in o s ccon 2. w a it for the oscill a tor to st a bilize. this c a n be a very long time when u sing the 32 khz oscill a tor. the a pplic a tion softw a re m u st ens u re th a t the del a y is long eno u gh for the oper a ting conditions 3. ch a nge ck s to switch the system clock so u rce. this t a kes a t most 2 periods of e a ch oscill a tor 4. dis a ble the previo u s oscill a tor by cle a ring the oscaen or oscben bits in o s ccon 5. note th a t u nlike at 8 9c51ic2, the o s cb so u rce is a ffected by both x2 a nd the ckrl divider. when ch a nging the clock so u rce, the x2 a nd ckrl v a l u es m a y need to be u pd a ted to a chieve the desired freq u ency the clock system h a rdw a re will prevent the dis a bling of the c u rrent a ctive oscill a tor a nd will pre- vent switching to a dis a bled oscill a tor. however, the h a rdw a re will not prevent switching to a n oscill a tor before it h a s st a bilized. the a pplic a tion softw a re m u st ens u re eno u gh del a y between en a bling a n oscill a tor a nd switching to th a t oscill a tor so th a t the oscill a tor so u rce c a n st a bilize. this is gener a lly only a n iss u e when u sing one of the cryst a l oscill a tors. 6.6.2 idle operation any en a bled oscill a tor will contin u e to f u nction d u ring idle mode. power c a n be red u ced by dis- a bling the a ltern a te oscill a tor before entering idle mode. once in idle mode, the oscill a tor so u rce c a nnot be ch a nged u ntil the mode is exited. an interr u pt exit from idle will le a ve the oscill a tor control bits (oscaen, oscben a nd ck s ) u nch a nged. any reset will exit idle mode a nd pl a ce these bits in their def au lt st a tes a s determined by the u ser f u se. 6.6.3 power-down operation all oscill a tors a re stopped d u ring power-down mode. once in power-down mode, the oscill a tor so u rce c a nnot be ch a nged u ntil the mode is exited. an interr u pt exit from po wer-down will le a ve the oscill a tor control bits (oscaen, oscben a nd ck s ) u nch a nged. any reset will exit power- down mode a nd pl a ce these bits in their def au lt st a tes a s determined by the u ser f u se. table 6-3. oscill a tor reset s t a tes control bit oscillator select fuse (hsb.osc) 00h (0) ffh (1) oscaen (o s ccon.0) 0 1 oscben (o ss con.1) 1 0 ck s (ck s el.0) 0 1
46 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.6.4 registers 6.7 x1/x2 feature the at 8 9lp51rb2/rc2/ic2 incl u des the x1/x2 fe a t u re for comp a tibility with the existing at 8 9c51rb2/rc2/ic2. this fe a t u re a llows a divider-by-2 to be switched in/o u t between the oscill a tor so u rce a nd the m a in system clock. this fe a t u re is controlled by the x2 bit in ckcon0 ( s ee t a ble 6-9 on p a ge 4 8 ). when x2 = 0 the system clock is divided by two from the oscill a tor so u rce, ens u ring a 50% d u ty cycle reg a rdless of the cyclic r a tio a t the oscill a tor o u tp u t. when x2 = 1 the oscill a tor o u tp u t is p a ssed thro u gh with no division. in this c a se the d u ty cycle a t the oscill a tor m u st be between 40% a nd 60%. note th a t the n a ming convention c a n be conf u sing since x1 me a ns divide-by-2 a nd x2 me a ns divide-by-1 a s shown in t a ble 6-7 . the def au lt st a te of the x2 bit is set by the x2 user f u se ( s ee s ection 24.2 on p a ge 1 88 ) b u t c a n a lw a ys be ch a nged by softw a re. this f u se is a lso sh a dowed in the x2 bit of the bootlo a der h a rdw a re s ec u - rity byte (h s b). note th a t the f u se/h s b bit is inverted from the control bit in the ckcon0 s fr. table 6-4. ck s el ? clock s election register ck s el = 8 5h (at 8 9lp51ic2 only) reset v a l u e = xxxx xxx?b not bit address a ble ??????? cks bit76543210 symbol function ck s clock select . cle a r ck s to connect the system clock (cpu a nd peripher a ls) to the o s cb so u rce. s et ck s to connect the system clock to the o s ca so u rce. the def au lt st a te is set by the oscill a tor s elect u ser f u se. s ee s ection 24.2 on p a ge 1 88 . table 6-5. o s ccon ? oscill a tor control register o s ccon = 8 6h (at 8 9lp51ic2 only) reset v a l u e = xxxx x0??b not bit address a ble ????? sclkt0 oscben oscaen bit76543210 symbol function s clkt0 sub clock timer 0 . cle a r to connect the timer 0 co u nter inp u t to t0 (p3.4). s et to connect the timer 0 co u nter inp u t to o s cb o u tp u t divided by 12 8 . o s cb m u st be so u rced from cryst a l oscill a tor b to u se this fe a t u re. oscben oscb enable . cle a r to power down the o s cb so u rce. s et to en a ble the o s cb so u rce. the def au lt st a te is set by the oscill a tor s elect u ser f u se. s ee s ection 24.2 on p a ge 1 88 . oscben c a nnot be dis a bled when ck s =0. dis a bling o s cb will free the xtal1b a nd xtal2b pins for u se a s p1.0 a nd p4.2. oscaen osca enable . cle a r to power down the o s ca so u rce. s et to en a ble the o s ca so u rce. the def au lt st a te is set by the oscill a tor s elect u ser f u se. s ee s ection 24.2 on p a ge 1 88 . oscaen c a nnot be dis a bled when ck s =1. table 6-6. x1/x2 modes mode x2 (ckcon0.0) cpu clock xtal1 duty cycle x2 fuse (hsb.x2) x1 0 f cpu = f s y s /2 no limits ffh (1) x2 1 f cpu = f s y s /1 40?60% 00h (0)
47 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.8 system clock prescaler the at 8 9lp51rb2/rc2/ic2 incl u des a n 8 -bit presc a ler th a t a llows the system clock to be divided down from the selected clock so u rce by even n u mbers in the r a nge 4?1020 in x1 mode a nd 2?510 in x2 mode. the presc a ler c a n red u ce power cons u mption by decre a sing the oper a - tion a l freq u ency d u ring non-critic a l periods. the presc a ler is implemented a s a n 8 -bit co u nter with relo a d. upon overflow from ffh to 00h the co u nter is relo a ded with the v a l u e of the ckrl register. when ckrl = ffh the presc a ler is dis a bled. the res u lting system freq u ency is given by the following eq ua tions where f o s c is the freq u ency of the selected clock so u rce a nd x2 is the v a l u e of ckcon0.0: the clock divider will presc a le the clock for the cpu a nd a ll peripher a ls. the v a l u e of ckrl m a y be ch a nged a t a ny time witho u t interr u pting norm a l exec u tion. ch a nges to ckrl will t a ke a ffect on the next presc a ler overflow. when ckrl is u pd a ted, the new freq u ency will t a ke a ffect within a m a xim u m period of 1024 x t o s c . the presc a ler is dis a bled by reset. f s y s f o s c 2 x2 4 255 ckrl ? () ----------------------------------------------- = ckrl 255 < () f s y s f o s c 2 x2 2 ---------------------------- = ckrl 255 = () table 6-7. ckrl ? clock relo a d register ckrl = 97h reset v a l u e = 1111 1111b not bit address a ble ckrl7 ckrl6 ckrl5 ckrl4 ckrl3 ckrl2 ckrl1 ckrl0 bit76543210 symbol function ckrl 7-0 clock reload . ckrl holds the relo a d v a l u e for the 8 -bit system clock presc a ler. when ckrl = ffh the presc a ler is dis a bled a nd no division is u sed. for a ll other v a l u es, the presc a ler co u nts u p to ffh a nd is relo a ded with the v a l u e of ckrl on the overflow to 00h. e a ch overflow of the presc a ler will toggle the system clock. ch a nges to ckrl will t a ke a ffect on the next overflow. table 6-8. clkreg ? clock register clkreg = aeh reset v a l u e = 0101 xxxxb not bit address a ble tp s 3tp s 2tp s 1tp s 0???? bit76543210 symbol function tp s 3-0 timer prescaler . the timer presc a ler selects the time b a se for timer 0, timer 1, timer 2, pca a nd the w a tchdog timer. the presc a ler is implemented a s a 4-bit bin a ry down co u nter. when the co u nter re a ches zero it is relo a ded with the v a l u e stored in the tp s bits to give a division r a tio between 1 a nd 16. by def au lt tp s is set to 5 for co u nting every six cycles (at 8 9c51rb2/rc2/ic2 comp a tibility). the presc a ler is a lw a ys en a bled in comp a tibility mode. in f a st mode the presc a ler is off by def au lt a nd c a n be individ ua lly en a bled for the peripher a ls thro u gh the ckcon0 a nd ckcon1 s frs.
48 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.9 peripheral clocks the b a se peripher a l clock is the s a me a s the cpu clock. it is a ffected by both the x2 setting a nd the ckrl presc a ler. however, individ ua l peripher a ls c a n h a ve their clock f u rther modified u sing the timer presc a ler in the clkreg register a nd the clock selection bits in the ckcon0 a nd ckcon1 registers. the timer presc a ler is a 4-bit presc a ler controlled by the tp s bits in clkreg ( s ee t a ble 6- 8 on p a ge 47 ). this presc a ler is sh a red a mong a ll peripher a ls a nd con- trols the co u nting r a te of timer 0, timer 1, timer 2, the pca timer a nd the w a tchdog. by def au lt the timers will co u nt every cpu clock cycle in f a st mode (tp s = 0000b) a nd every six cpu cycles in comp a tibility mode (tp s = 0101b). the bits in ckcon0 a nd ckcon1 select how the timer presc a ler a ffects e a ch peripher a l. in comp a tibility mode these bits decide if a f u rther divide-by-two is incl u ded in a ddition to the pres- c a ler. this a llows a device in x2 mode to u se peripher a ls th a t still r u n in x1 mode, i.e. x2 c a n be en a bled to speed u p the cpu witho u t needing to u pd a te the peripher a l b au d r a tes, overflow periods, etc. peripher a ls not a ffected by the timer presc a ler switch between the cpu clock a nd the cpu clock divided-by-2. in f a st mode the bits in ckcon0 a nd ckcon1 t u rn the timer presc a ler on/off for e a ch periph- er a l. the following eq ua tions show the peripher a l clock r a tes in comp a tibility mode a nd f a st mode where ?x2 is a peripher a ls bit in ckcon0 or ckcon1. an overview of the peripher a l clock selection is given in fig u re 6-7 on p a ge 49 . f peripheral f cpu 2 ?x2 tp s 1 + () -------------------------------------------- - = comp a tibility mode f peripheral f cpu tp s 1 + -------------------- - = f a st mode a nd ?x2 = 1 table 6-9. ckcon0 ? clock control register 0 ckcon0 = 8 fh reset v a l u e = 0000 000?b not bit address a ble twix2 wdx2 pcax2 s ix2 t2x2 t1x2 t0x2 x2 bit76543210 symbol function twix2 two-wire clock. in comp a tibility mode, cle a r for one system clock period per peripher a l clock cycle a nd set for two clock periods per peripher a l clock cycle (only v a lid when x2 = 1). in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit only a ffects the gener a ted s cl r a te d u ring twi m a ster mode. wdx2 watchdog clock . in comp a tibility mode, cle a r for tp s +1 system clock periods per peripher a l clock cycle a nd set for 2(tp s +1) clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit a ffects the w a tchdog timeo u t period. pcax2 programmable counter array clock . this bit a ffects the pca timer increment r a te a nd depends on cp s in cmod. cps 1-0 =00b : in comp a tibility mode, cle a r for tp s +1 system clock periods per peripher a l clock cycle a nd set for 2(tp s +1) clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. cps 1-0 =01b : in comp a tibility mode, cle a r for one system cloc k period per peripher a l clock cycle a nd set for two clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle.
49 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 6-7. peripher a l clock s election s ix2 uart clock . in comp a tibility mode, cle a r for one system clock period per peripher a l clock cycle a nd set for two clock periods per peripher a l clock cycle (only v a lid when x2 = 1). in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit a ffects the gener a ted b au d r a te d u ring modes 0 a nd 2. t2x2 timer 2 clock . in comp a tibility mode, cle a r for tp s +1 system clock periods per peripher a l clock cycle a nd set for 2(tp s +1) clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit a ffects the timer increment/decrement r a te. t1x2 timer 1 clock . in comp a tibility mode, cle a r for tp s +1 system clock periods per peripher a l clock cycle a nd set for 2(tp s +1) clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit a ffects the timer increment r a te. t0x2 timer 0 clock . in comp a tibility mode, cle a r for tp s +1 system clock periods per peripher a l clock cycle a nd set for 2(tp s +1) clock periods per peripher a l clock cycle. in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit a ffects the timer increment r a te. x2 cpu clock . in comp a tibility mode, cle a r for 12 clock periods per m a chine cycle a nd set for 6 clock periods per m a chine cycle. in f a st mode, cle a r for two clock periods per instr u ction cycle a nd set for one clock periods per instr u ction cycle. the def au lt st a te of x2 is set by the x2 f u se. s ee s ection 24.2 on p a ge 1 88 . symbol function system clock 2 0 1 t0x2 (tps+1) timer 0 2 0 1 timer 1 t1x2 0 1 timer 2 t2x2 0 1 watchdog wdx2 0 1 pca (cps = 00b) pcax2 0 1 pca (cps = 01b) pcax2 six2 & x2 uart 0 1 spix2 & x2 spi 0 1 twix2 & x2 twi 0 1 system clock 0 1 t0x2 (tps+1) timer 0 2 0 1 timer 1 t1x2 0 1 timer 2 t2x2 0 1 watchdog wdx2 0 1 pca (cps = 00b) pcax2 0 1 pca (cps = 01b) pcax2 six2 & x2 uart 0 1 spix2 & x2 spi 0 1 twix2 & x2 twi 0 1 fa s t mode compati b ility mode
50 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 6.10 timer subclock (at89l51ic2) when o s cb of at 8 9lp51ic2 is en a bled a nd so u rced from the low-freq u ency cryst a l oscill a tor, it c a n drive the co u nter inp u t of timer 0 in pl a ce of the t0 pin by setting the s clkt0 bit in o s c- con. the co u nter inp u t will be toggled a t the oscill a tor freq u ency divided by 12 8 . for this mode to f u nction correctly, the timer peripher a l clock m u st be r u nning (not in power-down) a nd oper a t- ing a t a freq u ency a t le a st twice a s high a s the s u bclock a s shown in the following eq ua tion: this req u irement is d u e to the f a ct th a t the timer m u st still s a mple the s u bclock edges the s a me a s if were s a mpling the t0 pin. this fe a t u re is not a v a il a ble when o s cb is so u rced from either the extern a l clock on xtal1b or the intern a l oscill a tor. pin t2 is a lso sh a red with the xtal1b pin. when o s bc is en a bled in the cryst a l oscill a tor or extern a l clock modes, t2 will toggle a t the oscill a tor freq u ency. timer 2 c a n then u se the oscill a - tor a s its co u nter inp u t a s well, with no division. for this mode to f u nction correctly, the timer peripher a l clock m u st be r u nning (not in power-down) a nd oper a ting a t a freq u ency a t le a st twice a s high o s cb a s shown in the following eq ua tion: table 6-10. ckcon1 ? clock control register 1 ckcon1 = afh reset v a l u e = xxxx xxx0b not bit address a ble ??????? s pix2 bit76543210 symbol function s pix2 spi clock . in comp a tibility mode, cle a r for one system clock period per peripher a l clock cycle a nd set for two clock periods per peripher a l clock cycle (only v a lid when x2 = 1). in f a st mode, cle a r for one system clock period a nd set for tp s +1 clocks per peripher a l clock cycle. this bit only a ffects the gener a ted s ck r a te d u ring s pi m a ster mode. timer 0 su bclock: f timer0 f xtal1b 64 ------------------ - su bclock: f timer2 f xtal1b 2
51 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 7. reset d u ring reset, a ll i/o registers a re set to their initi a l v a l u es, the port pins a re set to their def au lt mode, a nd the progr a m st a rts exec u tion from the reset vector, 0000h. the at 8 9lp51rb2/rc2/ic2 h a s six so u rces of reset: power-on reset, brown-o u t reset, extern a l reset, h a rdw a re w a tchdog reset, pca w a tchdog reset a nd softw a re reset. figure 7-1. reset su bsystem di a gr a m 7.1 power-on reset a power-on reset (por) is gener a ted by a n on-chip detection circ u it. the detection level v por is nomin a lly 1.4v. the por is a ctiv a ted whenever v dd is below the detection level. the por cir- c u it c a n be u sed to trigger the st a rt- u p reset or to detect a m a jor s u pply volt a ge f a il u re. the por circ u it ens u res th a t the device is reset from power-on. a power-on seq u ence is shown in fig u re 7-2 . when v dd re a ches the power-on reset threshold volt a ge v por , a n initi a liz a tion seq u ence l a sting t por is st a rted. when the initi a liz a tion seq u ence completes, the st a rt- u p timer determines how long the device is kept in por a fter v dd rise. the st a rt- u p timer does not begin co u nting u ntil a fter v dd re a ches the brown-o u t detector (bod) threshold volt a ge v bod . the por sign a l is a ctiv a ted a g a in, witho u t a ny del a y, when v dd f a lls below the por threshold level. a power-on reset (i.e. a cold reset) will set the pof fl a g in pcon. the intern a lly gener a ted reset c a n be extended beyond the power-on period by holding the r s t pin a ctive longer th a n the time-o u t. the st a rt- u p timer del a y is u ser-config u r a ble with the s t a rt- u p time user f u ses a nd depends on the clock so u rce ( t a ble 7-1 ). the s t a rt-up time f u ses a lso control the length of the st a rt- u p time a fter a brown-o u t reset or when w a king u p from power-down d u ring intern a lly timed mode. the st a rt- u p del a y sho u ld be selected to provide eno u gh settling time for v dd a nd the selected clock so u rce. the device oper a ting environment (s u pply volt a ge, freq u ency, temper a t u re, etc.) m u st meet the minim u m system req u irements before the device exits reset a nd st a rts norm a l oper a - tion. the r s t pin m a y be held a ctive extern a lly u ntil these conditions a re met. while the por is a ctive a reset o u tp u t p u lse will be gener a ted on the r s t pin to reset the bo a rd- level circ u itry. the o u tp u t p u lse is either open-dr a in or open-so u rce a s shown in fig u re 7-4 . in order to properly prop a g a te this p u lse to the rest of the bo a rd in the c a se of a n extern a l c a p a citor or power-s u pply s u pervisor circ u it, a 1 k resistor sho u ld be pl a ced in series with a ny extern a l driving circ u itry a s shown in fig u re 7-5 . the por o u tp u t p u lse c a nnot be dis a bled. por bod disrto rst internal re s et hardware watchdog pca watchdog software re s et
52 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 7-2. power-on reset s eq u ence note: t por is a pproxim a tely 143 s 5%. 7.2 brown-out reset the at 8 9lp51rb2/rc2/ic2 h a s a n on-chip brown-o u t detection (bod) circ u it for monitoring the v dd level d u ring oper a tion by comp a ring it to a fixed trigger level. the trigger level v bod for the bod is nomin a lly 2.0v. the p u rpose of the bod is to ens u re th a t if v dd f a ils or dips while exec u ting a t speed, the system will gr a cef u lly enter reset witho u t the possibility of errors ind u ced by incorrect exec u tion. a bod seq u ence is shown in fig u re 7-3 . when v dd decre a ses to a v a l u e below the trigger level v bod , the intern a l reset is immedi a tely a ctiv a ted. when v dd incre a ses a bove the trigger level pl u s a bo u t 200 mv of hysteresis, the st a rt- u p timer rele a ses the intern a l reset a fter the specified time-o u t period h a s expired ( t a ble 7-1 ). the bod does not gener a te a reset o u tp u t p u lse except a s p a rt of a por event. table 7-1. s t a rt- u p timer s ettings sut fuse 1 sut fuse 0 clock source t sut ( 5%) s 00 intern a l rc/extern a l clock 16 cryst a l oscill a tor 1024 01 intern a l rc/extern a l clock 512 cryst a l oscill a tor 204 8 10 intern a l rc/extern a l clock 1024 cryst a l oscill a tor 4096 11 intern a l rc/extern a l clock 4096 cryst a l oscill a tor 163 8 4 v dd r s t time-o u t t por t rhd v por intern a l reset r s t intern a l reset v il t s ut v bod (r s t left u nconnected) (r s t extended extern a lly) pol (pol tied to vcc) v il o u tp u t o u tp u t inp u t
53 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 7-3. brown-o u t detector reset the at 8 9lp51rb2/rc2/ic2 a llows for a wide v dd oper a ting r a nge. the on-chip bod m a y not be s u fficient to prevent incorrect exec u tion if v bod is lower th a n the minim u m req u ired v dd r a nge, s u ch a s when a 5.0v s u pply is co u pled with high freq u ency oper a tion. in s u ch c a ses a n extern a l brown-o u t reset circ u it connected to the r s t pin m a y be req u ired. 7.3 external reset the r s t pin of the at 8 9lp51rb2/rc2/ic2 c a n f u nction a s either a n a ctive-low reset inp u t or a s a n a ctive-high reset inp u t. the pol a rity of the r s t pin is select a ble u sing the pol pin (for- merly ea ). when pol is high the r s t pin is a ctive high with a n on-chip p u ll-down resistor tied to gnd. when pol is low the r s t pin is a ctive low with a n on-chip p u ll- u p resistor tied to v dd . the r s t pin str u ct u re is shown in fig u re 7-4 . entry into reset is completely a synchrono u s. the pres- ence of the a ctive reset level on the inp u t will immedi a tely reset the device. a glitch filter will s u ppress a ll reset inp u t p u lses of less th a n 50 ns. exit from reset is synchrono u s. in comp a tibil- ity mode the reset pin is s a mpled every six clock cycles a nd m u st be held in a ctive for a t le a st twelve clock cycles to de a ssert the intern a l reset. in f a st mode the reset pin is s a mpled every clock cycle a nd m u st be held in a ctive for a t le a st two clock cycles to de a ssert the intern a l reset. the at 8 9lp51rb2/rc2/ic2 incl u des a n on-chip power-on reset a nd brown-o u t detector cir- c u it th a t ens u res th a t the device is reset from system power u p. in most c a ses a rc st a rt u p circ u it is not req u ired on the r s t pin, red u cing system cost, a nd the r s t pin m a y be left u ncon- nected if a bo a rd-level reset is not present. note: r s t a lso serves a s the in- s ystem progr a mming (i s p) en a ble. i s p is en a bled when the extern a l reset pin is held a ctive. when i s p is dis a bled by f u se, i s p m a y only be entered by p u lling r s t a ctive d u ring power- u p. if this beh a vior is necess a ry, it is recommended to u se a n a ctive-low reset so th a t i s p c a n be entered by shorting r s t to gnd a t power- u p. figure 7-4. reset pin s tr u ct u re v dd time-o u t v por intern a l reset t s ut v bod v cc disrto wdt reset rst internal reset pol = 1 v cc disrto wdt reset rst internal reset pol = 0
54 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 7.4 hardware watchdog reset when the h a rdw a re w a tchdog times o u t, it will gener a te a reset p u lse l a sting 49 clock cycles. by def au lt this p u lse is a lso o u tp u t on the r s t pin. the o u tp u t p u lse is either open-dr a in or open-so u rce a s shown in fig u re 7-4 . in order to properly prop a g a te this p u lse to the rest of the bo a rd in the c a se of a n extern a l c a p a citor or power-s u pply s u pervisor circ u it, a 1 k resistor sho u ld be pl a ced in series with a ny extern a l driving circ u itry a s shown in fig u re 7-5 . to dis a ble the r s t o u tp u t the di s rto bit in the wdtprg register m u st be set to one. w a tchdog reset will set the wdtovf fl a g in wdtprg. to prevent a w a tchdog reset, the w a tchdog reset seq u ence 1eh/e1h m u st be written to wdtr s t before the w a tchdog times o u t. s ee s ection 16. on p a ge 104 for det a ils on the oper a tion of the w a tchdog. figure 7-5. recommended reset o u tp u t s chem a tics 7.5 pca watchdog reset mod u le 4 of the progr a mm a ble co u nter arr a y (pca) c a n be config u red a s a w a tchdog timer. when a comp a re m a tch occ u rs between mod u le 4 a nd the pca timer, it will gener a te a n intern a l reset p u lse l a sting 16 clock cycles. this p u lse is never o u tp u t on the r s t pin. s ee s ection 15.7 on p a ge 104 for det a ils on the oper a tion of the pca w a tchdog. 7.6 software reset the cpu m a y gener a te a 49-clock cycle reset p u lse by writing the softw a re reset seq u ence 5ah/a5h to the wdr s t register. a softw a re reset will set the s wr s t bit in wdtprg. s ee ? s oftw a re reset? on p a ge 105 for more inform a tion on softw a re reset. writing a ny seq u ences other th a n 5ah/a5h or 1eh/e1h to wdtr s t will gener a te a n immedi a te reset a nd set both wdtovf a nd s wr s t to fl a g a n error. s oftw a re reset will a lso drive the r s t pin a ctive u nless di s rto is set. rst pol = 1 at 8 9lp51xd2 to other on-board circuitry 1 k vcc + rst vcc rst pol = 0 at 8 9lp51xd2 to other on-board circuitry 1 k + rst vcc
55 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 8. power saving modes the at 8 9lp51rb2/rc2/ic2 s u pports two different softw a re select a ble power-red u cing modes: idle a nd power-down. these modes a re a ccessed thro u gh the pcon register. addition a l steps m a y be req u ired to a chieve the lowest possible power cons u mption while u sing these modes. in a ddition the at 8 9lp51rb2/rc2/ic2 h a s f u sible config u r a tion options th a t c a n f u rther red u ce the a ctive power cons u mption u nder cert a in circ u mst a nces. 8.1 idle mode s etting the idl bit in pcon enters idle mode. idle mode h a lts the intern a l cpu clock. the cpu st a te is preserved in its entirety, incl u ding the ram, st a ck pointer, progr a m co u nter, progr a m st a t u s word, a nd a cc u m u l a tor. the port pins hold the logic st a tes they h a d a t the time th a t idle w a s a ctiv a ted. idle mode le a ves the peripher a ls r u nning in order to a llow them to w a ke u p the cpu when a n interr u pt is gener a ted. the timer a nd uart peripher a ls contin u e to f u nction d u r- ing idle. if these f u nctions a re not needed d u ring idle, they sho u ld be explicitly dis a bled by cle a ring the a ppropri a te control bits in their respective s frs. the w a tchdog m a y be selectively en a bled or dis a bled d u ring idle by setting/cle a ring the wdidle bit. the brown-o u t detector is a lw a ys a ctive d u ring idle. any en a bled interr u pt so u rce or reset m a y termin a te idle mode. when exiting idle mode with a n interr u pt, the interr u pt will immedi a tely be serviced, a nd following reti the next instr u ction to be exec u ted will be the one following the instr u ction th a t p u t the device into idle. the power cons u mption d u ring idle mode c a n be f u rther red u ced by presc a ling down the system clock u sing the s ystem clock presc a ler ( s ection 6. 8 on p a ge 47 ). be a w a re th a t the clock divider will a ffect a ll peripher a l f u nctions a nd b au d r a tes m a y need to be a dj u sted to m a int a in their r a te with the new clock freq u ency. . table 8-1. pcon ? power control register pcon = 8 7h reset v a l u e = 000x 0000b not bit address a ble s mod1 s mod0 pwdex pof gf1 gf0 pd idl bit76543210 symbol function s mod1 do u ble b au d r a te bit. do u bles the b au d r a te of the uart in modes 1, 2, or 3. s mod0 fr a me error s elect. when s mod0 = 1, s con.7 is s m0. when s mod0 = 1, s con.7 is fe. note th a t fe will be set a fter a fr a me error reg a rdless of the st a te of s mod0. pwdex power-down exit mo de. when pwdex = 0, w a ke u p from power-down is extern a lly controlled. when pwdex = 1, w a ke u p from power-down is intern a lly timed. pof power off fl a g. pof is set to ?1? d u ring power u p (i.e. cold reset). it c a n be set or reset u nder softw a re control a nd is not a ffected by r s t or bod (i.e. w a rm resets). gf1, gf0 gener a l-p u rpose fl a gs pd power-down bit. s etting this bit a ctiv a tes power-down oper a tion. the pd bit is cle a red au tom a tic a lly by h a rdw a re when w a king u p from power-down. idl idle mode bit. s etting this bit a ctiv a tes idle mode oper a tion. the idl bit is cle a red au tom a tic a lly by h a rdw a re when w a king u p from idle
56 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 8.2 power-down mode s etting the power-down (pd) bit in pcon enters power-down mode. power-down mode stops the oscill a tor, dis a bles the bod a nd powers down the fl a sh memory in order to minimize power cons u mption. only the power-on circ u itry will contin u e to dr a w power d u ring power-down. d u r- ing power-down, the power s u pply volt a ge m a y be red u ced to the ram keep- a live volt a ge. the ram contents will be ret a ined, b u t the s fr contents a re not g ua r a nteed once v dd h a s been red u ced. power-down m a y be exited by extern a l reset, power-on reset, or cert a in en a bled interr u pts. 8.2.1 interrupt recovery from power-down two extern a l interr u pt so u rces m a y be config u red to termin a te power-down mode: extern a l interr u pts int0 (p3.2) a nd int1 (p3.3). to w a ke u p by extern a l interr u pt int0 or int1 , th a t inter- r u pt m u st be en a bled by setting ex0 or ex1 in ie a nd m u st be config u red for level-sensitive oper a tion by cle a ring it0 or it1. when termin a ting power-down by a n interr u pt, two different w a ke- u p modes a re a v a il a ble. when pwdex in pcon is one, the w a ke- u p period is intern a lly timed a s shown in fig u re 8 -1 . at the f a lling edge on the interr u pt pin, power-down is exited, the oscill a tor is rest a rted, a nd a n intern a l timer begins co u nting. the intern a l clock will not be a llowed to prop a g a te to the cpu u ntil a fter the timer h a s timed o u t. after the time-o u t period the interr u pt service ro u tine will begin. the time-o u t period is controlled by the s t a rt- u p timer f u ses (see t a ble 7-1 on p a ge 52 ). the interr u pt pin need not rem a in low for the entire time-o u t period. figure 8-1. interr u pt recovery from power-down (pwdex = 1) when pwdex = ?0?, the w a ke- u p period is controlled extern a lly by the interr u pt. ag a in, a t the f a lling edge on the interr u pt pin, power-down is exited a nd the oscill a tor is rest a rted. however, the intern a l clock will not prop a g a te u ntil the rising edge of the interr u pt pin a s shown in fig u re 8 - 2 . the interr u pt pin sho u ld be held low long eno u gh for the selected clock so u rce to st a bilize. after the rising edge on the pin the interr u pt service ro u tine will be exec u ted. pwd int1 xtal1 t s ut intern a l clock
57 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 8-2. interr u pt recovery from power-down (pwdex = 0) 8.2.2 reset recovery from power-down the w a ke- u p from power-down thro u gh a n extern a l reset is simil a r to the interr u pt with pwdex = ?1?. at the rising edge of r s t, power-down is exited, the oscill a tor is rest a rted, a nd a n intern a l timer begins co u nting a s shown in fig u re 8 -3 . the intern a l clock will not be a llowed to prop a g a te to the cpu u ntil a fter the timer h a s timed o u t. the time-o u t period is controlled by the s t a rt- u p timer f u ses. ( s ee t a ble 7-1 on p a ge 52 ). if r s t ret u rns low before the time-o u t, a two clock cycle intern a l reset is gener a ted when the intern a l clock rest a rts. otherwise, the device will rem a in in reset u ntil r s t is bro u ght low. figure 8-3. reset recovery from power-down (pol = 1) 8.3 reducing power consumption s ever a l possibilities need consider a tion when trying to red u ce the power cons u mption in a n 8 051-b a sed system. ? idle or power-down mode sho u ld be u sed a s often a s possible with interr u pts w a king u p the system to h a ndle specific t a sks ? all u n-needed peripher a l f u nctions sho u ld be dis a bled ?the s ystem clock presc a ler c a n sc a le down the oper a ting freq u ency d u ring periods of low dem a nd ( s ee ? s ystem clock presc a ler? on p a ge 47 .) ? the ale o u tp u t c a n be dis a bled by setting ao in auxr, thereby a lso red u cing emi ?for at 8 9lp51ic2, switch the system clock from a high power oscill a tor like xtala to a lower power oscill a tor like the intern a l 8 mhz oscill a tor d u ring periods when freq u ency a cc u r a cy is not a s import a nt. pwd int1 xtal1 intern a l clock pwd r s t xtal1 t s ut intern a l clock intern a l reset
58 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 8.4 low power configuration s ever a l of the nonvol a tile user config u r a tion f u ses c a n en a ble modes where less power will be cons u med d u ring norm a l oper a tion a s listed in t a ble 8 -2 . these f u ses m u st gener a lly be set once by a n extern a l progr a mmer to m a tch the desired oper a ting environment. ? for cryst a l freq u encies of 12 mhz or less, o s ca sho u ld be pl a ced in low power cryst a l oscill a tor mode ?x1 mode is s u pported for comp a tibility with existing a pplic a tions. x2 mode sho u ld be u sed to a chieve the s a me cpu a nd peripher a l speed a t h a lf the cryst a l freq u ency ? the low power mode settings ch a nge the slope a nd intercept of the a ctive c u rrent vers u s freq u ency rel a tionship. s ee t a ble 8 -3 below. table 8-2. user config u r a tion f u ses affecting power cons u mption fuse name description clock s o u rce a the low power cryst a l oscill a tor (setting 2) will u se h a lf the power of the high s peed cryst a l oscill a tor (setting 3) for the s a me freq u ency ( 12 mhz) x2 mode x2 mode c a n keep the s a me cpu speed while c u tting the cryst a l freq u ency in h a lf. low power mode low power mode c a n red u ce the power cons u mption for system freq u encies u nder 20 mhz. extr a low power mode c a n f u rther red u ce the power if the system freq u ency is less th a n 1 mhz. table 8-3. low power mode f u ses fuse 1 (0eh) fuse 0 (0dh) mode description 00h (0) ffh (1) extr a low power lowest power mode. use only if the oscill a tor freq u ency c a n never be a bove 1 mhz. ffh (1) ffh (0) low power low power mode will red u ce cons u mption for cpu freq u encies u nder 10 mhz a nd slightly incre a se cons u mption for cpu freq u encies over 10 mhz comp a red to norm a l mode. this mode is best for oscill a tor freq u encies below 10 mhz or for freq u encies 10?20 mhz where the presc a ler m a y be u sed to sc a le the cpu freq u ency below 10 mhz. ? 00h (0) norm a l norm a l mode h a s higher cons u mption th a n low power mode for cpu freq u encies u nder 10 mhz b u t slightly less cons u mption for cpu freq u encies over 10 mhz. this mode is best for oscill a tor freq u encies over 20 mhz or for freq u encies 10?20 mhz where the presc a ler is not u sed to sc a le the cpu freq u ency.
59 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 9. interrupts the at 8 9lp51rb2/rc2/ic2 provides 11 interr u pt vectors: two extern a l interr u pts (int0 a nd int1 ), three timer interr u pts (timers 0, 1 a nd 2), a seri a l port interr u pt, a n s pi interr u pt, a key- bo a rd interr u pt, a pca interr u pt, a n a n a log comp a r a tor interr u pt a nd a n adc interr u pt. these interr u pts a nd the system reset e a ch h a ve a sep a r a te progr a m vector a t the st a rt of the progr a m memory sp a ce. e a ch interr u pt so u rce c a n be individ ua lly en a bled or dis a bled by setting or cle a ring a bit in the interr u pt en a ble registers: ien0 a nd ien1. the ien0 register a lso cont a ins a glob a l dis a ble bit, ea, which dis a bles a ll interr u pts. all of the bits th a t gener a te interr u pts c a n be set or cle a red by softw a re, with the s a me res u lt a s tho u gh they h a d been set or cle a red by h a rdw a re. th a t is, interr u pts c a n be gener a ted a nd pending interr u pts c a n be c a nceled in softw a re. 9.1 interrupt priority e a ch interr u pt so u rce c a n be individ ua lly progr a mmed to one of fo u r priority levels by setting or cle a ring bits in the interr u pt priority registers: ipl0, ipl1, iph0 a nd iph1. ipl0 a nd ipl1 hold the low order priority bits a nd iph0 a nd iph1 hold the high priority bits for e a ch interr u pt a s shown in t a ble 9-2 . an interr u pt service ro u tine in progress c a n be interr u pted by a higher priority inter- r u pt, b u t not by a nother interr u pt of the s a me or lower priority. the highest priority interr u pt c a nnot be interr u pted by a ny other interr u pt so u rce. if two req u ests of different priority levels a re pending a t the end of a n instr u ction, the req u est of higher priority level is serviced. if req u ests of the s a me priority level a re pending a t the end of a n instr u ction, a n intern a l polling seq u ence determines which req u est is serviced. the polling seq u ence is b a sed on the vector a ddress; a n interr u pt with a lower vector a ddress h a s higher priority th a n a n interr u pt with a higher vector a ddress, except in the c a se of the pca, whose polling priority is moved u p by two a s shown in t a ble 9-1 a nd fig u re 9-1 . note th a t the polling seq u ence is only u sed to resolve pending req u ests of the s a me priority level. table 9-1. interr u pt vector addresses a nd priority polling priority interrupt source vector address 0 s ystem reset r s t or por or bod 0000h 1 extern a l interr u pt 0 ie0 0003h 2 timer 0 overflow tf0 000bh 3 extern a l interr u pt 1 ie1 0013h 4 timer 1 overflow tf1 001bh 6 s eri a l port interr u pt ri or ti 0023h 7 timer 2 interr u pt tf2 or exf2 002bh 5 pca interr u pt cf, ccf0, ccf1, ccf2, ccf3 or ccf4 0033h 8 keybo a rd interr u pt kbf 7-0 003bh 9 two-wire interr u pt s i 0043h 10 s pi interr u pt s pif or modf or txe 004bh 11 reserved 0053h 12 an a log comp a r a tor interr u pt cfa or cfb 005bh 13 adc interr u pt adif 0063h
60 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 9-1. interr u pt control su bsystem table 9-2. priority level bit v a l u es iph.x ipl.x interrupt priority level 0 0 0 (lowest) 011 102 1 1 3 (highest) tf0 ea int0 iphx, iplx ien1, ien0 ea ea ea ea ea ea ea it0 ie0 int1 it1 ie1 tf1 pca it ri ti tf2 exf2 kbd it ea ea twif spif modf txe ea ea cfa cfb adif ex0 et0 ex1 et1 ec es et2 ekbd etwi espi ecmp eadc 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 high priority interrupt low priority interrupt glo b al di s a b le individual ena b le interrupt polling se q uence, decrea s ing from high to low priority
61 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 9.2 interrupt response the interr u pt fl a gs m a y be set by their h a rdw a re in a ny clock cycle. the interr u pt controller polls the fl a gs in the l a st clock cycle of the instr u ction in progress. if one of the fl a gs w a s set in the preceding cycle, the po lling cycle will find it a nd the interr u pt system will gener a te a n lcall to the a ppropri a te service ro u tine a s the next instr u ction, provided th a t the interr u pt is not blocked by a ny of the following conditions: ?an interr u pt of eq ua l or higher priority level is a lre a dy in progress ? the instr u ction in progress is reti or a ny write to the ienx, iplx or iphx registers e a ch of these conditions will block the gener a tion of the lcall to the interr u pt service ro u tine. the second condition ens u res th a t if the instr u ction in progress is reti or a ny a ccess to ienx, iplx or iphx, then a t le a st one more instr u ction will be exec u ted before a ny interr u pt is vectored to. the polling cycle is repe a ted a t the l a st cycle of e a ch instr u ction, a nd the v a l u es polled a re the v a l u es th a t were present a t the previo u s clock cycle. if a n a ctive interr u pt fl a g is not being serviced bec au se of one of the a bove conditions a nd is no longer a ctive when the blocking condition is removed, the denied interr u pt will not be serviced. in other words, the f a ct th a t the interr u pt fl a g w a s once a ctive b u t not serviced is not remember ed. every polling cycle is new. if a req u est is a ctive a nd conditions a re met for it to be a cknowledged, a h a rdw a re s u bro u tine c a ll to the req u ested service ro u tine will be the next instr u ction exec u ted. the c a ll itself t a kes fo u r cycles. th u s, a minim u m of five complete clock cycles el a psed between a ctiv a tion of a n interr u pt req u est a nd the beginning of exec u tion of the first instr u ction of the service ro u tine. a longer response time res u lts if the req u est is blocked by one of the previo u sly listed conditions. if a n interr u pt of eq ua l or higher priority level is a lre a dy in progress, the a ddition a l w a it time depends on the n a t u re of the other interr u pt's service ro u tine. if the instr u ction in progress is not in its fin a l clock cycle, the a ddition a l w a it time c a nnot be more th a n 4 cycles, since the longest instr u ction is 5 cycles long. if the instr u ction in progress is reti, the a ddition a l w a it time c a nnot be more th a n 9 cycles ( a m a xim u m of 4 more cycles to complete the instr u ction in progress, pl u s a m a xim u m of 5 cycles to complete the next instr u ction). th u s, in a single-interr u pt system, the response time is a lw a ys more th a n 5 clock cycles a nd less th a n 14 clock cycles. s ee fig u re 9-2 a nd fig u re 9-3 . when a n interr u pt is serviced, its interr u pt fl a g m u st be cle a red before the reti instr u ction or else the interr u pt will contin u e to be gener a ted. m a ny interr u pt vectors h a ve m u ltiple so u rces. the service ro u tine norm a lly m u st determine which fl a g bit gener a ted the interr u pt a nd th a t bit m u st be cle a red by softw a re. if m u ltiple so u rce bits a re set for one interr u pt, the interr u pt will contin u e to be gener a ted u ntil a ll the so u rce bits h a ve been cle a red. in some c a ses the interr u pt fl a gs is cle a red by h a rdw a re when the interr u pt is a cknowledged. the extern a l interr u pts int0 a nd int1 c a n e a ch be either level- a ctiv a ted or edge- a ctiv a ted, depending on bits it0 a nd it1 in register tcon. the fl a gs th a t a ct ua lly gener a te these inter- r u pts a re the ie0 a nd ie1 bits in tcon. when the service ro u tine is vectored to, h a rdw a re cle a rs the fl a g th a t gener a ted a n extern a l interr u pt only if the interr u pt w a s edge- a ctiv a ted. if the inter- r u pt w a s level a ctiv a ted, then the extern a l req u esting so u rce (r a ther th a n the on-chip h a rdw a re) controls the req u est fl a g. the timer 0 a nd timer 1 interr u pts a re gener a ted by tf0 a nd tf1, which a re set by a rollover in their respective timers). when a timer interr u pt is gener a ted, the on-chip h a rdw a re cle a rs the fl a g th a t gener a ted it when the service ro u tine is vectored to. all other fl a gs m u st be cle a red by softw a re.
62 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 9-2. minim u m interr u pt response time (f a st mode) figure 9-3. m a xim u m interr u pt response time (f a st mode) figure 9-4. minim u m interr u pt response time (comp a tibility mode) figure 9-5. m a xim u m interr u pt response time (comp a tibility mode) clock cycles int0 ie0 15 instr u ction lcall 1st i s r instr. c u r. instr. ack. clock cycles int0 ie0 1 14 instr u ction reti movx @/dptr, a lcall 1st i s r instr. ack. 510 clock cycles int0 ie0 1 instr u ction lcall i s r ack. 14 clock cycles int0 ie0 1 instr u ction reti mul ab lcall i s r ack. 13 37 49
63 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 9.3 interrupt registers table 9-3. ien0 ? interr u pt en a ble register 0 ien0 = a 8 h reset v a l u e = 0000 0000b bit address a ble ea ec et2 e s et1 ex1 et0 ex0 bit76543210 symbol function ea global interrupt enable all interr u pts a re dis a bled when ea = 0. when ea = 1, e a ch interr u pt so u rce is en a bled/dis a bled by setting /cle a ring its own en a ble bit. ec pca interrupt enable cle a r to dis a ble the pca interr u pt. s et to en a ble the pca interr u pt when ea = 1. et2 timer 2 interrupt enable cle a r to dis a ble the timer 2 interr u pt. s et to en a ble the timer 2 interr u pt when ea = 1. e s serial port interrupt enable cle a r to dis a ble the uart interr u pt. s et to en a ble the uart interr u pt when ea = 1. et1 timer 1 interrupt enable cle a r to dis a ble the timer 1 interr u pt. s et to en a ble the timer 1 interr u pt when ea = 1. ex1 external interrupt 1 enable. cle a r to dis a ble the int1 interr u pt. s et to en a ble the int1 interr u pt when ea = 1. et0 timer 0 interrupt enable cle a r to dis a ble the timer 0 interr u pt. s et to en a ble the timer 0 interr u pt when ea = 1. ex0 external interrupt 0 enable cle a r to dis a ble the int0 interr u pt. s et to en a ble the int0 interr u pt when ea = 1. table 9-4. ien1 ? interr u pt en a ble register 1 ien1 = b1h reset v a l u e = 0000 0000b bit address a ble ? ? eadc ecmp ? e s pi etwi ekbd bit76543210 symbol function eadc adc interrupt enable. cle a r to dis a ble the adc interr u pt. s et to en a ble the adc interr u pt when ea = 1. ecmp analog comparator interrupt enable cle a r to dis a ble the an a log comp a r a tor interr u pt. s et to en a ble the an a log comp a r a tor interr u pt when ea = 1. e s pi spi interrupt enable cle a r to dis a ble the s pi interr u pt. s et to en a ble the s pi interr u pt when ea = 1. etwi twi interrupt enable cle a r to dis a ble the twi interr u pt. s et to en a ble the twi interr u pt when ea = 1. ekbd keyboard interrupt enable cle a r to dis a ble the keybo a rd interr u pt. s et to en a ble the keybo a rd interr u pt when ea = 1.
64 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 9-5. ipl0 ? interr u pt priority low register 0 ipl0 = b 8 h reset v a l u e = 0000 0000b bit address a ble ip0di s ppcl pt2l p s l pt1l px1l pt0l px0l bit76543210 symbol function ip0di s interrupt level 0 disable cle a r to en a ble a ll interr u pts with priority level 0. s et to dis a ble a ll interr u pts with priority level 0. ppcl pca interrupt priority low low order bit for pca interr u pt priority level. pt2l timer 2 interrupt priority low low order bit for timer 2 interr u pt priority level. p s l serial port interrupt priority low low order bit for uart interr u pt priority level. pt1l timer 1 interrupt priority low low order bit for timer 1 interr u pt priority level. px1l external interrupt 1 priority low low order bit for int1 interr u pt priority level. pt0l timer 0 interrupt priority low low order bit for timer 0 interr u pt priority level. px0l external interrupt 0 priority low low order bit for int0 interr u pt priority level. table 9-6. ipl1 ? interr u pt priority low register 1 ipl1 = b2h reset v a l u e = 0000 0000b bit address a ble ip2di s ? padcl pcmpl ? p s pl ptwl pkbl bit76543210 symbol function ip2di s interrupt level 2 disable cle a r to en a ble a ll interr u pts with priority level 2. s et to dis a ble a ll interr u pts with priority level 2. padcl adc interrupt priority low low order bit for adc interr u pt priority level. pcmpl analog comparator interrupt priority low low order bit for an a log comp a r a tor interr u pt priority level. p s pl spi interrupt priority low low order bit for s pi interr u pt priority level. ptwl twi interrupt priority low low order bit for twi interr u pt priority level. pkbl keyboard interrupt priority low low order bit for keybo a rd interr u pt priority level.
65 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 9-7. iph0 ? interr u pt priority high register 0 iph0 = b7h reset v a l u e = 0000 0000b not bit address a ble ip1di s ppch pt2h p s h pt1h px1h pt0h px0h bit76543210 symbol function ip1di s interrupt level 1 disable cle a r to en a ble a ll interr u pts with priority level 1. s et to dis a ble a ll interr u pts with priority level 1. ppch pca interrupt priority high high order bit for pca interr u pt priority level. pt2h timer 2 interrupt priority high high order bit for timer 2 interr u pt priority level. p s h serial port interrupt priority high high order bit for uart interr u pt priority level. pt1h timer 1 interrupt priority high high order bit for timer 1 interr u pt priority level. px1h external interrupt 1 priority high high order bit for int1 interr u pt priority level. pt0h timer 0 interrupt priority high high order bit for timer 0 interr u pt priority level. px0h external interrupt 0 priority high high order bit for int0 interr u pt priority level. table 9-8. iph1 ? interr u pt priority high register 1 iph1 = b3h reset v a l u e = 0000 0000b not bit address a ble ip3di s ? padch pcmph ? p s ph ptwh pkbh bit76543210 symbol function ip3di s interrupt level 3 disable cle a r to en a ble a ll interr u pts with priority level 3. s et to dis a ble a ll interr u pts with priority level 3. padch adc interrupt priority high high order bit for adc interr u pt priority level. pcmph analog comparator interrupt priority high high order bit for an a log comp a r a tor interr u pt priority level. p s ph spi interrupt priority high high order bit for s pi interr u pt priority level. ptwh twi interrupt priority high high order bit for twi interr u pt priority level. pkbh keyboard interrupt priority high high order bit for keybo a rd interr u pt priority level.
66 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 10. external interrupts the int0 (p3.2) a nd int1 (p3.3) pins of the at 8 9lp51rb2/rc2/ic2 m a y be u sed a s extern a l interr u pt so u rces. the extern a l interr u pts c a n be progr a mmed to be level- a ctiv a ted or tr a nsition- a ctiv a ted by setting or cle a ring bit it1 or it0 in register tcon. if itx = 0, extern a l interr u pt x is triggered by a detected low a t the intx pin. if itx = 1, extern a l interr u pt x is edge-triggered. in this mode if s u ccessive s a mples of the intx pin show a high in one cycle a nd a low in the next cycle, interr u pt req u est fl a g iex in tcon is set. fl a g bit iex then req u ests the interr u pt. s ince the extern a l interr u pt pins a re s a mpled once e a ch clock cycle, a n inp u t high or low sho u ld hold for a t le a st 2 system periods to ens u re s a mpling. if the extern a l interr u pt is tr a nsition- a cti- v a ted, the extern a l so u rce h a s to hold the req u est pin high for a t le a st two clock cycles, a nd then hold it low for a t le a st two clock cycles to ens u re th a t the tr a nsition is seen so th a t interr u pt req u est fl a g iex will be set. iex will be au tom a tic a lly cle a red by the cpu when the service ro u - tine is c a lled if gener a ted in edge-triggered mode. if the extern a l interr u pt is level- a ctiv a ted, the extern a l so u rce h a s to hold the req u est a ctive u ntil the req u ested interr u pt is a ct ua lly gener a ted. then the extern a l so u rce m u st de a ctiv a te the req u est before the interr u pt service ro u tine is com- pleted, or else a nother interr u pt will be gener a ted. both int0 a nd int1 m a y w a ke u p the device from the power-down st a te. other peripher a l pins c a n a lso gener a te interr u pts in response to a n extern a l event: ? a neg a tive edge on the t2ex pin (p1.1) c a n set the exf2 fl a g in t2con ?tr a nsitions on the pca c a pt u re inp u ts cex0?cex4 (p1.3?7) c a n set the ccfx bits in ccon ?tr a nsitions or levels on port 1 c a n set the bits in kbf u sing the keybo a rd interf a ce (see next section). 11. keyboard interface and general-purpose interrupts the at 8 9lp51rb2/rc2/ic2 implements a keybo a rd interf a ce a llowing the connection of a 1xn to 8 x n m a trix keybo a rd. the keybo a rd f u nction provides 8 config u r a ble extern a l interr u pts on port 1. e a ch port pin c a n detect high/low levels or positive/neg a tive edges. the keybo a rd inp u ts a re considered a s 8 independent interr u pt so u rces sh a ring the s a me interr u pt vector. the kbe register selects which bits of port 1 a re en a bled to gener a te a n interr u pt. the kbmod a nd kbl s registers determine the mode for e a ch individ ua l pin. kbmod selects between level-sensitive a nd edge-triggered mode. kbl s selects between high/low in level mode a nd positive/neg a tive in edge mode. a block di a gr a m is shown in fig u re 11-1 . the pins of port 1 a re s a mpled every clock cycle. in level-sensitive mode, a v a lid level m u st a ppe a r in two s u ccessive s a mples before gener a ting the interr u pt. in edge-triggered mode, a tr a nsition will be detected if the v a l u e ch a nges from one s a mple to the next. when a n interr u pt condition on a pin is detected, a nd th a t pin is en a bled, the a ppropri a te fl a g in the kbf register is set. the fl a gs in kbf m u st be cle a red by softw a re. any en a bled keybo a rd interr u pt m a y w a ke u p the device from the idle or power-down st a te. unlike at 8 9c51rb2/rc2/ic2 the fl a gs in kbf a re not cle a red by re a ding the register. the soft- w a re m a y cle a r e a ch bit individ ua lly or a ll a t once. this a llows the interf a ce to be u sed for gener a l p u rpose extern a l interr u pts where some fl a gs c a n be left pending between c a lls to the service ro u tine. e a ch fl a g c a n a lso be m a de pending by softw a re by writing a one to it. to a chieve the s a me beh a vior a s at 8 9c51rb2/rc2/ic2, the service ro u tine m u st cle a r the entire register.
67 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 11-1. keybo a rd block di a gr a m d q 2 2 2 2 0 0 1 1 (p1.2) gpi2 d q 1 1 1 1 0 0 1 1 (p1.1) gpi1 d q 0 0 0 0 0 0 1 1 (p1.0) gpi0 d q 3 3 3 3 0 0 1 1 (p1. 3 ) gpi 3 d q 6 6 6 6 0 0 1 1 (p1.6) gpi6 d q 5 5 5 5 0 0 1 1 (p1.5) gpi5 d q 4 4 4 4 0 0 1 1 (p1.4) gpi4 d q 7 7 7 7 0 0 1 1 (p1.7) gpi7 kbmod kbls kbe kbf interrupt clk
68 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 11.1 registers . . . table 11-1. kbmod ? keybo a rd mode register kbmod = 9fh reset v a l u e = 0000 0000b not bit address a ble kbmod7 kbmod6 kbmod5 kbmod4 kbmod3 kbmod2 kbmod1 kbmod0 bit76543210 kbmod.x 0 = level-sensitive interr u pt for p1.x 1 = edge-triggered interr u pt for p1.x table 11-2. kbl s ? keybo a rd level s elect register kbl s = 9ch reset v a l u e = 0000 0000b not bit address a ble kbl s 7 kbl s 6 kbl s 5 kbl s 4 kbl s 3kbl s 2 kbl s 1 kbl s 0 bit76543210 kbl s .x 0 = detect low level or neg a tive edge on p1.x 1 = detect high level or positive edge on p1.x table 11-3. kbe ? keybo a rd interr u pt en a ble register kbe = 9dh reset v a l u e = 0000 0000b not bit address a ble kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit76543210 kbe.x 0 = interr u pt for p1.x dis a bled 1 = interr u pt for p1.x en a bled table 11-4. kbf ? keybo a rd interr u pt fl a g register kbf = 9eh reset v a l u e = 0000 0000b not bit address a ble kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit76543210 kbf.x 0 = interr u pt on p1.x in a ctive 1 = interr u pt on p1.x a ctive. m u st be cle a red by softw a re.
69 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 12. i/o ports the at 8 9lp51rb2/rc2/ic2 c a n be config u red for between 36 a nd 40 i/o pins. the ex a ct n u m- ber of gener a l i/o pins a v a il a ble depends on the clock a nd extern a l memory config u r a tion a s shown in t a ble 12-1 . note: on at 8 9lp51ic2 o s cb req u ires 0, 1 or 2 i/o pins depending on the clock s o u rce b setting. dis- a bling o s cb (oscben = 0) frees u p the o s cb pins for gener a l u se. dis a bling o s ca (oscaen = 0) does not free u p the o s ca pins. o s ca m u st be config u red for intern a l rc mode to u se these pins even when r u nning from o s cb only. 12.1 port configuration all port pins on the at 8 9lp51rb2/rc2/ic2 m a y be config u red in one of fo u r modes: q ua si-bidi- rection a l (st a nd a rd 8 051 port o u tp u ts), p u sh-p u ll o u tp u t, open-dr a in o u tp u t, or inp u t-only. port modes m a y be a ssigned in softw a re on a pin-by-pin b a sis a s shown in t a ble 12-2 u sing the reg- isters listed in t a ble 12-3 . the trist a te-port user f u se ( s ee s ection 24.2 on p a ge 1 88 ) determines the def au lt st a te of the port pins. when the f u se is en a bled, a ll port pins on p1, p2 a nd p3 def au lt to inp u t-only mode a fter reset. when the f u se is dis a bled, a ll port pins on p1, p2 a nd p3 def au lt to q ua si-bidirection a l mode a fter reset a nd a re we a kly p u lled high. p0 a lw a ys def au lts to open-dr a in mode. p4.4?5 a lw a ys def au lt to q ua si-bidirection a l mode. p4.0?1 a lw a ys def au lt to open-dr a in. the other pins of p4 obey the f u se. e a ch port pin a lso h a s a s chmitt-triggered inp u t for improved inp u t noise rejection. d u ring power-down a ll the s chmitt-triggered inp u ts a re dis a bled with the exception of p3.2 (int0 ), p3.3 (int1 ), r s t, p 4 . 6 ( x ta l 1 ) a nd p4.7 (xtal2). therefore, p3.2, p3.3, p4.6 a nd p4.7 sho u ld not be left flo a ting d u ring power-down. n a ddition a ny pin of port 1 config u red a s a keybo a rd inter- r u pt inp u t will a lso rem a in a ctive d u ring power-down to w a ke- u p the device. these interr u pt pins sho u ld either be dis a bled before entering power-down or they sho u ld not be left flo a ting. table 12-1. at 8 9lp51rb2/rc2 i/o pin config u r a tions clock source a external program access external data access number of i/o pins extern a l cryst a l or reson a tor ye s ( p s en+ale+p0+p2) yes (rd+wr) 1 8 no 20 no 8 -bit (ale+rd+wr+p0) 27 16-bit (ale+rd+wr+p0) 19 no 3 8 extern a l clock ye s ( p s en+ale+p0+p2) yes (rd+wr) 19 no 21 no 8 -bit (ale+rd+wr+p0) 2 8 16-bit (ale+rd+wr+p0+p2) 20 no 39 intern a l rc oscill a tor ye s ( p s en+ale+p0+p2) yes (rd+wr) 20 no 22 no 8 -bit (ale+rd+wr+p0) 29 16-bit (ale+rd+wr+p0+p2) 21 no 40
70 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary . . . 12.1.1 quasi-bidirectional output port pins in q ua si-bidirection a l o u tp u t mode f u nction simil a r to st a nd a rd 8 051 port pins. a q ua si- bidirection a l port c a n be u sed both a s a n inp u t a nd o u tp u t witho u t the need to reconfig u re the port. this is possible bec au se when the port o u tp u ts a logic high, it is we a kly driven, a llowing a n extern a l device to p u ll the pin low. when the pin is driven low, it is driven strongly a nd a ble to sink a l a rge c u rrent. there a re three p u ll- u p tr a nsistors in the q ua si-bidirection a l o u tp u t th a t serve different p u rposes. one of these p u ll- u ps, c a lled the ?very we a k? p u ll- u p, is t u rned on whenever the port l a tch for the pin cont a ins a logic ?1?. this very we a k p u ll- u p so u rces a very sm a ll c u rrent th a t will p u ll the pin high if it is left flo a ting. when the pin is p u lled low extern a lly this p u ll- u p will a lw a ys so u rce some c u rrent. the very we a k p u ll- u p is dis a bled when the port register cont a ins a zero. in a ddition the very we a k p u ll- u ps of a ll q ua si-bidirection a l ports c a n be dis a bled glob a lly by setting the dpu bit in the auxr register ( s ee t a ble 3-2 on p a ge 19 ). table 12-2. config u r a tion modes for port x pin y pxm0.y pxm1.y port mode 00q ua si-bidirection a l 01p u sh-p u ll o u tp u t 10inp u t only (high imped a nce) 1 1 open-dr a in o u tp u t table 12-3. port config u r a tion registers port port data port configuration 0p0 ( 8 0h) p0m0 (d4h), p0m1 (d5h) 1 p1 (90h) p1m0 (e6h), p1m1 (e7h) 2 p2 (a0h) p2m0 (d6h), p2m1 (d7h) 3 p3 (b0h) p3m0 (deh), p3m1 (cfh) 4 p4 (c0h) p4m0 (beh), p4m1 (bfh) table 12-4. port config u r a tion reset v a l u es register tristate ports fuse = ffh (1) tristate ports fuse = 00h (0) p0m0 ff ff p0m1 ff ff p1m0 ff 00 p1m1 00 00 p2m0 ff 00 p2m1 00 00 p3m0 ff 00 p3m1 00 00 p4m0 c7 03 p4m0 03 03
71 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary a second p u ll- u p, c a lled the ?we a k? p u ll- u p, is t u rned on when the port l a tch for the pin cont a ins a logic ?1? a nd the pin itself is a lso a t a logic ?1? level. this p u ll- u p provides the prim a ry so u rce c u rrent for a q ua si-bidirection a l pin th a t is o u tp u tting a ?1?. if this pin is p u lled low by a n extern a l device, this we a k p u ll- u p t u rns off, a nd only the very we a k p u ll- u p rem a ins on. in order to p u ll the pin low u nder these conditions, the extern a l device h a s to sink eno u gh c u rrent to overpower the we a k p u ll- u p a nd p u ll the port pin below its inp u t threshold volt a ge. the third p u ll- u p is referred to a s the ?strong? p u ll- u p. this p u ll- u p is u sed to speed u p low-to- high tr a nsitions on a q ua si-bidirection a l port pin when the port l a tch ch a nges from a logic ?0? to a logic ?1?. when this occ u rs, the strong p u ll- u p t u rns on for one cpu clock, q u ickly p u lling the port pin high. the q ua si-bidirection a l port config u r a tion is shown in fig u re 12-1 . 12.1.2 input-only mode the inp u t only port config u r a tion is shown in fig u re 12-2 . the o u tp u t drivers a re trist a ted. the inp u t incl u des a s chmitt-triggered inp u t for improved inp u t noise rejection. the inp u t circ u itry of p3.2, p3.3, p4.6 a nd p4.7 is not dis a bled d u ring power-down (see fig u re 12-3 ) a nd therefore these pins sho u ld not be left flo a ting d u ring power-down when config u red in this mode. inp u t-only mode c a n red u ce power cons u mption for low-level inp u ts over q ua si-bidirection a l mode bec au se the ?very we a k? p u ll- u p is t u rned off a nd only very sm a ll le a k a ge c u rrent in the s u b micro a mp r a nge is present. figure 12-1. q ua si-bidirection a l o u tp u t figure 12-2. inp u t only figure 12-3. inp u t circ u it for p3.2, p3.3, p4.6 a nd p4.7 1 clo c k del a y (d flip-flop) s trong v e r y w e a k w e a k p o r t pin v cc v cc v cc f rom p o r t register inp u t d a t a pwd p o r t pin inp u t d a t a pwd port pin inp u t d a t a
72 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 12.1.3 open-drain output the open-dr a in o u tp u t config u r a tion t u rns off a ll p u ll- u ps a nd only drives the p u ll-down tr a nsistor of the port pin when the port l a tch cont a ins a logic ?0?. to be u sed a s a logic o u tp u t, a port con- fig u red in this m a nner m u st h a ve a n extern a l p u ll- u p, typic a lly a resistor tied to v dd . the p u ll- down for this mode is the s a me a s for the q ua si-bidirection a l mode. the open-dr a in port config u - r a tion is shown in fig u re 12-4 . the inp u t circ u itry of p3.2, p3.3, p4.6 a nd p4.7 is not dis a bled d u ring power-down (see fig u re 12-3 ) a nd therefore these pins sho u ld not be left flo a ting d u ring power-down when config u red in this mode. figure 12-4. open-dr a in o u tp u t 12.1.4 push-pull output the p u sh-p u ll o u tp u t config u r a tion h a s the s a me p u ll-down str u ct u re a s both the open-dr a in a nd the q ua si-bidirection a l o u tp u t modes, b u t provides a contin u o u s strong p u ll- u p when the port l a tch cont a ins a logic ?1?. the p u sh-p u ll mode m a y be u sed when more so u rce c u rrent is needed from a port o u tp u t. the p u sh-p u ll port config u r a tion is shown in fig u re 12-5 . figure 12-5. p u sh-p u ll o u tp u t 12.2 port analog functions the at 8 9lp51rb2/rc2/ic2 incorpor a tes two a n a log comp a r a tors a nd a n 8 -ch a nnel a n a log-to- digit a l converter. in order to give the best a n a log perform a nce a nd minimize power cons u mp- tion, pins th a t a re being u sed for a n a log f u nctions m u st h a ve both their digit a l o u tp u ts a nd digit a l inp u ts dis a bled. digit a l o u tp u ts a re dis a bled by p u tting the port pins into the inp u t-only mode a s described in ?port config u r a tion? on p a ge 69 . the a n a log inp u t pins will a lw a ys def au lt to inp u t- only mode a fter reset reg a rdless of the st a te of the trist a te-port f u se. p o r t pin f rom p o r t register inp u t d a t a pwd p o r t pin v cc f rom p o r t register inp u t d a t a pwd
73 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary digit a l inp u ts on p2.4, p2.5, p2.6 a nd p2.7 a re dis a bled whenever a n a n a log comp a r a tor is en a bled by setting the cena or cenb bits in ac s ra a nd ac s rb a nd th a t pin is config u red for inp u t-only mode. to u se a n a n a log inp u t pin a s a high-imped a nce digit a l inp u t while a comp a r a - tor is en a bled, th a t pin sho u ld be config u red in open-dr a in mode a nd the corresponding port register bit sho u ld be set to 1. digit a l inp u ts on port 0 a re dis a bled for e a ch pin config u red for inp u t-only mode whenever the adc is en a bled by setting the adce bit a nd cle a ring the dac bit in dadc. to u se a ny port 0 inp u t pin a s a high-imped a nce digit a l inp u t while the adc is en a bled, th a t pin sho u ld be config- u red in open-dr a in mode a nd the corresponding port register bit sho u ld be set to 1. when dac mode is en a bled, p2.2 a nd p2.3 a re forced to inp u t-only mode. 12.3 port read-modify-write a re a d from a port will re a d either the st a te of the pins or the st a te of the port register depending on which instr u ction is u sed. s imple re a d instr u ctions will a lw a ys a ccess the port pins directly. re a d-modify-write instr u ctions, which re a d a v a l u e, possibly modify it, a nd then write it b a ck, will a lw a ys a ccess the port register. this incl u des bit write instr u ctions s u ch a s clr or s etb a s they a ct ua lly re a d the entire port, modify a single bit, then write the d a t a b a ck to the entire port. s ee t a ble 12-5 for a complete list of re a d-modify-write instr u ction which m a y a ccess the ports. 12.4 port alternate functions most gener a l-p u rpose digit a l i/o pins of the at 8 9lp51rb2/rc2/ic2 sh a re f u nction a lity with the v a rio u s i/os needed for the peripher a l u nits. t a ble 12-7 lists the a ltern a te f u nctions of the port pins. altern a te f u nctions a re connected to the pins in a logic and f a shion. in order to en a ble the a ltern a te f u nction on a port pin, th a t pin m u st h a ve a ?1? in its corresponding port register bit, otherwise the inp u t/o u tp u t will a lw a ys be ?0?. however, a ltern a te f u nctions m a y be tempor a rily forced to ?0? by cle a ring the a ssoci a ted port bit, provided th a t the pin is not in inp u t-only mode. f u rthermore, e a ch pin m u st be config u red for the correct inp u t/o u tp u t mode a s req u ired by its peripher a l before it m a y be u sed a s s u ch. t a ble 12-6 shows how to config u re a generic pin for u se with a n a ltern a te f u nction. if two or more port pins on the s a me 8 -bit req u ire difference direc- tions, the port m u st be config u red for bidirection a l oper a tion. table 12-5. port re a d-modify-write instr u ctions mnemonic instruction example anl logic a l and anl p1, a orl logic a l or orl p1, a xrl logic a l ex-or xrl p1, a jbc j u mp if bit set a nd cle a r bit jbc p3.0, label cpl complement bit cpl p3.1 inc increment inc p1 dec decrement dec p3 djnz decrement a nd j u mp if not zero djnz p3, label mov px.y, c move c a rry to bit y of port x mov p1.0, c clr px.y cle a r bit y of port x clr p1.1 s etb px.y s et bit y of port x s etb p3.2
74 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 12-6. pin f u nction config u r a tions for port x pin y pxm0.y pxm1.y px.y i/o mode 0 0 1 bidirection a l (intern a l p u ll- u p) 01 1o u tp u t 10 xinp u t 1 1 1 bidirection a l (extern a l p u ll- u p) table 12-7. port pin altern a te f u nctions port pin configuration bits alternate function notes pxm0.y pxm1.y p0.0 p0m0.0 p0m1.0 ad0 a u tom a tic config u r a tion adc0 inp u t-only p0.1 p0m0.1 p0m1.1 ad1 a u tom a tic config u r a tion adc1 inp u t-only p0.2 p0m0.2 p0m1.2 ad2 a u tom a tic config u r a tion adc2 inp u t-only p0.3 p0m0.3 p0m1.3 ad3 a u tom a tic config u r a tion adc3 inp u t-only p0.4 p0m0.4 p0m1.4 ad4 a u tom a tic config u r a tion adc4 inp u t-only p0.5 p0m0.5 p0m1.5 ad5 a u tom a tic config u r a tion adc5 inp u t-only p0.6 p0m0.6 p0m1.6 ad6 a u tom a tic config u r a tion adc6 inp u t-only p0.7 p0m0.7 p0m1.7 ad7 a u tom a tic config u r a tion adc7 inp u t-only p1.0 p1m0.0 p1m1.0 t2 o s cb m u st be dis a bled or in intern a l oscill a tor mode (at 8 9lp51ic2) gpi0 xtal1b p1.1 p1m0.1 p1m1.1 t2ex ss remap = 0 gpi1 p1.2 p1m0.2 p1m1.2 eci gpi2 p1.3 p1m0.3 p1m1.3 cex0 gpi3
75 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary p1.4 p1m0.4 p1m1.4 ss remap = 1 gpi4 cex1 p1.5 p1m0.5 p1m1.5 mi s o remap = 0 mo s i remap = 1 cex2 gpi5 p1.6 p1m0.6 p1m1.6 s ck remap = 0 mi s o remap = 1 cex3 gpi6 p1.7 p1m0.7 p1m1.7 mo s i remap = 0 s ck remap = 1 cex4 gpi7 p2.0 p2m0.0 p2m1.0 a 8 p2.1 p2m0.1 p2m1.1 a9 p2.2 p2m0.2 p2m1.2 a10 da+ inp u t-only p2.3 p2m0.3 p2m1.3 a11 da- inp u t-only p2.4 p2m0.4 p2m1.4 a12 ain0 inp u t-only p2.5 p2m0.5 p2m1.5 a13 ain1 inp u t-only p2.6 p2m0.6 p2m1.6 a14 ain2 inp u t-only p2.7 p2m0.7 p2m1.7 a15 ain3 inp u t-only p3.0 p3m0.0 p3m1.0 rxd p3.1 p3m0.1 p3m1.1 txd p3.2 p3m0.2 p3m1.2 int0 p3.3 p3m0.3 p3m1.3 int1 p3.4 p3m0.4 p3m1.4 t0 p3.5 p3m0.5 p3m1.5 t1 p3.6 p3m0.6 p3m1.6 wr table 12-7. port pin altern a te f u nctions port pin configuration bits alternate function notes pxm0.y pxm1.y
76 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary p3.7 p3m0.7 p3m1.7 rd p4.0 p4m0.0 p4m1.0 s cl open-dr a in p4.1 p4m0.1 p4m1.1 s da open-dr a in p4.2 p4m0.2 p4m1.2 xtal2b o s cb m u st be dis a bled or in intern a l oscill a tor or extern a l clock modes to u se p4.2(at 8 9lp51ic2) p4.4 p4m0.4 p4m1.4 ale s et ao in auxr to u se p4.4 p4.5 p4m0.5 p4m1.5 p s en p4.6 p4m0.6 p4m1.6 xtal1a o s ca m u st be set to intern a l rc mode to u se p4.6 p4.7 p4m0.7 p4m1.7 xtal2a o s ca m u st be set to intern a l rc or extern a l clock modes to u se p4.7 table 12-7. port pin altern a te f u nctions port pin configuration bits alternate function notes pxm0.y pxm1.y
77 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 13. enhanced timer 0 and timer 1 with pwm the at 8 9lp51rb2/rc2/ic2 h a s two 16-bit timer/co u nters, timer 0 a nd timer 1, with the fol- lowing fe a t u res: ? two 16-bit timer/co u nters with 16-bit relo a d registers ? two independent 8 -bit precision pwm o u tp u ts with 8 -bit presc a lers ?uart or s pi b au d r a te gener a tion u sing timer 1 ?o u tp u t pin toggle on timer overflow ? s plit timer mode a llows for three sep a r a te timers (2 8 -bit, 1 16-bit) ?g a ted modes a llow timers to r u n/h a lt b a sed on a n extern a l inp u t timer 0 a nd timer 1 h a ve simil a r modes of oper a tion. as timers, the timer registers norm a lly incre a se every clock cycle. th u s, the registers co u nt clock cycles. the timer r a te c a n be pres- c a led by a v a l u e between 1 a nd 16 u sing the timer presc a ler (see s ection 6.9 on p a ge 4 8 ). both timers sh a re the s a me presc a ler. in comp a tibility mode the presc a ler is a lw a ys en a bled a nd tp s def au lts to 5, so the timers co u nt every six clock cycles (1/12 of the oscill a tor freq u ency in x1 mode or 1/6 of the oscill a tor freq u ency in x2 mode). in x2 mode the timers c a n be set to the x1 r a te by setting the t0x2 or t1x2 bits in ckcon1. in f a st mode the presc a ler is not en a bled by def au lt so the co u nt r a te is eq ua l to the system freq u ency (1/2 of the oscill a tor fre- q u ency in x1 mode or eq ua l to the oscill a tor freq u ency in x2 mode). in this c a se setting the t0x2 or t1x2 bits in ckcon1 en a bles the presc a ler for e a ch timer. as co u nters, the timer registers a re incremented in response to a 1-to-0 tr a nsition a t the corre- sponding inp u t pins, t0 or t1. in f a st mode the extern a l inp u t is s a mpled every clock cycle. when the s a mples show a high in one cycle a nd a low in the next cycle, the co u nt is incre- mented. the new co u nt v a l u e a ppe a rs in the register d u ring the cycle following the one in which the tr a nsition w a s detected. s ince 2 clock cycles a re req u ired to recognize a 1-to-0 tr a nsition, the m a xim u m co u nt r a te is 1/2 of the system freq u ency. there a re no restrictions on the d u ty cycle of the inp u t sign a l, b u t it sho u ld be held for a t le a st one f u ll clock cycle to ens u re th a t a given level is s a mpled a t le a st once before it ch a nges. in comp a tibility mode the co u nter inp u t s a mpling is controlled by the presc a ler. s ince tp s def au lts to 6 in this mode, the pins a re s a mpled every six system clocks. therefore the inp u t sig- n a l sho u ld be held for a t le a st six clock cycles to ens u re th a t a given level is s a mpled a t le a st once before it ch a nges. f u rthermore, the timer or co u nter f u nctions for timer 0 a nd timer 1 h a ve fo u r oper a ting modes: 13-bit timer, 16-bit timer, 8 -bit au to-relo a d timer, a nd split timer. the control bits c/t in the s pe- ci a l f u nction register tmod select the timer or co u nter f u nction. the bit p a irs (m1, m0) in tmod select the oper a ting modes. f timer f s y s 2 tnx2 tp s 1 + () ----------------------------------------------- - = comp a tibility mode f timer f s y s tp s 1 + -------------------- - = f a st mode a nd tnx2 = 1 f timer f s y s = f a st mode a nd tnx2 = 0
78 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 13.1 registers t a ble 13-1 lists the registers u sed by timer 0/1. tcon, tconb a nd tmod a re det a iled below. note: the rhn/rln registers a re not req u ired by the timer d u ring modes 0, 2 or 3 a nd m a y be u sed a s tempor a ry stor a ge registers in these modes, except when u sing the pwm gener a tor. . table 13-1. timer 0/1 register su mm a ry name address purpose bit-addressable tcon 88 h control y tmod 8 9h mode n tl0 8 ah timer 0 low-byte n tl1 8 bh timer 1 low-byte n th0 8 ch timer 0 high-byte n th1 8 dh timer 1 high-byte n tconb 91h mode n rl0 f2h timer 0 relo a d low-byte n rl1 f3h timer 1 relo a d low-byte n rh0 f4h timer 0 relo a d high-byte n rh1 f5h timer 1 relo a d high-byte n table 13-2. tcon ? timer/co u nter control register tcon = 88 h reset v a l u e = 0000 0000b bit address a ble tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit76543210 symbol function tf1 timer 1 overflow flag s et by h a rdw a re on timer/co u nter overflow. cle a red by h a rdw a re when the processor vectors to interr u pt ro u tine. tr1 timer 1 run control s et/cle a red by softw a re to t u rn timer/co u nter on/off. tf0 timer 0 overflow flag s et by h a rdw a re on timer/co u nter overflow. cle a red by h a rdw a re when the processor vectors to interr u pt ro u tine. tr0 timer 0 run control s et/cle a red by softw a re to t u rn timer/co u nter on/off. ie1 interrupt 1 edge flag s et by h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt processed. it1 interrupt 1 type s et/cle a red by softw a re to specify f a lling edge/low level triggered extern a l interr u pts. ie0 interrupt 0 edge flag s et by h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt processed. it0 interrupt 0 type s et/cle a red by softw a re to specify f a lling edge/low level triggered extern a l interr u pts.
79 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 13-3. tmod ? timer/co u nter mode control register tmod address = 0 8 9h reset v a l u e = 0000 0000b not bit address a ble gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m0 t0m1 bit76543210 symbol function gate1 timer 1 gating control when set, timer/co u nter 1 is en a bled only while int1 pin is high a nd tr1 control pin is set. when cle a red, timer 1 is en a bled whenever tr1 control bit is set. c/t1 timer or counter selector 1 cle a red for timer oper a tion (inp u t from intern a l system clock). s et for co u nter oper a tion (inp u t from t1 inp u t pin). c/t1 m u st be zero when u sing timer 1 in pwm o u tp u t mode. t1m1 t1m0 timer 1 operating mode mode t1m1 t1m0 operation 000 v a ri a ble timer mode. 8 -bit timer/co u nter th1 with tl1 a s 1? 8 bit presc a ler. def au lt is 5 bits for a 13-bit timer/co u nter comp a tible with at 8 9c51rb2/rc2/ic2. 101 16-bit a u to-relo a d mode. th1 a nd tl1 a re c a sc a ded to form a 16-bit timer/co u nter which is relo a ded from rh1 a nd rl1 when it overflows. 210 8 -bit a u to-relo a d mode. th1 holds a v a l u e which is relo a ded into 8 -bit timer/co u nter tl1 e a ch time it overflows. 311timer/co u nter 1 is stopped gate0 timer 0 gating control when set, timer/co u nter 0 is en a bled only while int0 pin is high a nd tr0 control pin is set. when cle a red, timer 0 is en a bled whenever tr0 control bit is set. c/t0 timer or counter selector 0 cle a red for timer oper a tion (inp u t from intern a l system clock). s et for co u nter oper a tion (inp u t from t0 inp u t pin). c/t0 m u st be zero when u sing timer 0 in pwm o u tp u t mode. t0m1 t0m0 timer 0 operating mode mode t0m1 t0m0 operation 000 v a ri a ble timer mode. 8 -bit timer/co u nter th0 with tl0 a s 1? 8 bit presc a ler. def au lt is 5 bits for a 13-bit timer/co u nter comp a tible with at 8 9c51rb2/rc2/ic2. 101 16-bit a u to-relo a d mode. th0 a nd tl0 a re c a sc a ded to form a 16-bit timer/co u nter which is relo a ded from rh0 a nd rl0 when it overflows. 210 8 -bit a u to-relo a d mode. th0 holds a v a l u e which is relo a ded into 8 -bit timer/co u nter tl0 e a ch time it overflows. 311 s plit timer mode. tl0 is a n 8 -bit timer/co u nter controlled by the st a nd a rd timer 0 control bits. th0 is only a n 8 -bit timer controlled by timer 1 control bits.
80 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 13.2 mode 0 ? variable width timer/counter both timers in mode 0 a re 8 -bit co u nters with a v a ri a ble presc a ler. the presc a ler m a y v a ry from 1 to 8 bits depending on the p s c bits in tconb, giving the timer a r a nge of 9 to 16 bits. by def au lt the timer is config u red a s a 13-bit timer comp a tible to mode 0 in the st a nd a rd 8 051. fig u re 13-1 shows the mode 0 oper a tion a s it a pplies to timer 1 in 13-bit mode. as the co u nt rolls over from a ll ?1?s to a ll ?0?s, it sets the timer interr u pt fl a g tf1. the co u nter inp u t is en a bled to the timer when tr1 = 1 a nd either gate1 = 0 or int1 =1. s etting gate1 = 1 a llows the timer to be controlled by extern a l inp u t int1 , to f a cilit a te p u lse width me a s u rements. tr1 is a control bit in the tcon register. gate1 is in tmod. the 13-bit register consists of a ll 8 bits of th1 a nd the lower 5 bits of tl1. the u pper 3 bits of tl1 a re indetermin a te a nd sho u ld be ignored. s etting the r u n fl a g (tr1) does not cle a r the registers. the following eq ua tion gives the timeo u t period for mode 0. in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will do u ble the timeo u t period. mode 0 oper a tion is the s a me for timer 0 a s for timer 1, except th a t tr0, tf0, gate0 a nd int0 repl a ce the corresponding timer 1 sign a ls in fig u re 13-1 . there a re two different c/t bits, one for timer 1 (tmod.6) a nd one for timer 0 (tmod.2). table 13-4. tconb ? timer/co u nter control register b tconb = 91h reset v a l u e = 0010 0100b not bit address a ble pwm1en pwm0en p s c12 p s c11 p s c10 p s c02 p s c01 p s c00 bit76543210 symbol function pwm1en pulse width modulation 1 enable s et to config u re timer 1 for p u lse width mod u l a tion o u tp u t on t1 (p3.5). cle a r to dis a ble t1 a s a n o u tp u t. pwm0en pulse width modulation 0 enable s et to config u re timer 0 for p u lse width mod u l a tion o u tp u t on t0 (p3.4). cle a r to dis a ble t0 a s a n o u tp u t. p s c12 p s c11 p s c10 timer 1 prescaler presc a ler for timer 1 mode 0. the n u mber of a ctive bits in tl1 eq ua ls p s c1 + 1. after reset p s c1 = 100b which en a bles 5 bits of tl1 for comp a tibility with the 13-bit mode 0 in at 8 9c51rb2/rc2/ic2. p s c02 p s c01 p s c00 timer 0 prescaler presc a ler for timer 0 mode 0. the n u mber of a ctive bits in tl0 eq ua ls p s c0 + 1. after reset p s c0 = 100b which en a bles 5 bits of tl0 for comp a tibility with the 13-bit mode 0 in at 8 9c51rb2/rc2/ic2. mode 0: time-o u t period 256 2 p s cn 1 + f s y s ---------------------------------------- - tp s 1 + () =
81 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 13-1. timer/co u nter 1 mode 0: v a ri a ble width co u nter 13.3 mode 1 ? 16-bit auto -reload timer/counter in mode 1 the timers a re config u red for 16-bit au to-relo a d. the timer register is r u n with a ll 16 bits. the 16-bit relo a d v a l u e is stored in the high a nd low relo a d registers (rh1/rl1). the clock is a pplied to the combined high a nd low timer registers (th1/tl1). as clock p u lses a re received, the timer co u nts u p: 0000h, 0001h, 0002h, etc. an overflow occ u rs on the ffffh-to- 0000h tr a nsition, u pon which the timer register is relo a ded with the v a l u e from rh1/rl1 a nd the overflow fl a g bit in tcon is set. s ee fig u re 13-2 . the relo a d registers def au lt to 0000h, which gives the f u ll 16-bit timer period comp a tible with the st a nd a rd 8 051. mode 1 oper a tion is the s a me for timer/co u nter 0. the following eq ua tion gives the timeo u t period for mode 1. in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will do u ble the timeo u t period. figure 13-2. timer/co u nter 1 mode 1: 16-bit a u to-relo a d clk s y s t1 pin tr1 gate1 int1 pin tl1 ( 8 bits) control inter r u p t c/t = 0 c/t = 1 p s c1 th1 ( 8 bits) tf1 tp s mode 1: time-o u t period 65536 rhn rln {,} ? () f s y s --------------------------------------------------------- tp s 1 + () = clk s y s t1 pin tr1 gate1 int1 pin tl1 ( 8 bits) control inter r u p t c/t = 0 c/t =1 th1 ( 8 bits) tf1 rl1 ( 8 bits) rh1 ( 8 bits) relo a d tp s
82 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 13.4 mode 2 ? 8-bit auto -reload timer/counter mode 2 config u res the timer register a s a n 8 -bit co u nter (tl1) with au tom a tic relo a d, a s shown in fig u re 13-3 . overflow from tl1 not only sets tf1, b u t a lso relo a ds tl1 with the contents of th1, which is preset by softw a re. the relo a d le a ves th1 u nch a nged. mode 2 oper a tion is the s a me for timer/co u nter 0. the following eq ua tion gives the timeo u t period for mode 2. in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will do u ble the timeo u t period. figure 13-3. timer/co u nter 1 mode 2: 8 -bit a u to-relo a d note: rh1/rl1 a re not req u ired by timer 1 d u ring mode 2 a nd m a y be u sed a s tempor a ry stor a ge registers. 13.5 mode 3 ? 8-bit split timer timer 1 in mode 3 simply holds its co u nt. the effect is the s a me a s setting tr1 = 0. timer 0 in mode 3 est a blishes tl0 a nd th0 a s two sep a r a te co u nters. the logic for mode 3 on timer 0 is shown in fig u re 13-4 . tl0 u ses the timer 0 control bits: c/t, gate0, tr0, int0 , a nd tf0. th0 is locked into a timer f u nction (co u nting clock cycles) a nd t a kes over the u se of tr1 a nd tf1 from timer 1. th u s, th0 now controls the timer 1 interr u pt. while timer 0 is in mode 3, timer 1 will still obey its settings in tmod b u t c a nnot gener a te a n interr u pt. mode 3 is for a pplic a tions req u iring a n extr a 8 -bit timer or co u nter. with timer 0 in mode 3, the at 8 9lp51rb2/rc2/ic2 c a n a ppe a r to h a ve fo u r timer/co u nters. when timer 0 is in mode 3, timer 1 c a n be t u rned on a nd off by switching it o u t of a nd into its own mode 3. in this c a se, timer 1 c a n still be u sed by the seri a l port a s a b au d r a te gener a tor or in a ny a pplic a tion not req u iring a n interr u pt. the following eq ua tion gives the timeo u t period for mode 3. in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will do u ble the timeo u t period. mode 2: time-o u t period 256 thn ? () f s y s ------------------------------- - tp s 1 + () = clk s y s t1 pin tr1 gate1 tf1 tl1 ( 8 bits) th1 ( 8 bits) control relo a d inter r u p t int0 pin c/t = 0 c/t = 1 tp s mode 3: time-o u t period 256 f s y s ----------- tp s 1 + () =
83 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 13-4. timer/co u nter 0 mode 3: two 8 -bit co u nters 13.6 pulse width modulation on the at 8 9lp51rb2/rc2/ic2, timer 0 a nd timer 1 m a y be independently config u red a s 8 -bit a symmetric a l (edge- a ligned) p u lse width mod u l a tors (pwm) by setting the pwm0en or pwm1en bits in tconb, respectively. in pwm mode the gener a ted w a veform is o u tp u t on the timer's inp u t pin, t0 or t1. therefore, c/tx m u st be set to ?0? when in pwm mode a nd the t0 (p3.4) a nd t1 (p3.5) m u st be config u red in a n o u tp u t mode. the timer overflow fl a gs a nd interr u pts will contin u e to f u nction while in pwm mode a nd timer 1 m a y still gener a te the b au d r a te for the uart. the timer gate f u nction a lso works in pwm mode, a llowing the o u tp u t to be h a lted by a n extern a l inp u t. e a ch pwm ch a nnel h a s fo u r modes selected by the mode bits in tmod. an ex a mple w a veform for timer 0 in pwm mode 0 is shown in fig u re 13-5 . th0 a cts a s a n 8 -bit co u nter while rh0 stores the 8 -bit comp a re v a l u e. when th0 is 00h the pwm o u tp u t is set high. when the th0 co u nt re a ches the v a l u e stored in rh0 the pwm o u tp u t is set low. therefore, the p u lse width is proportion a l to the v a l u e in rh0. to prevent glitches, writes to rh0 only t a ke effect on the ffh to 00h overflow of th0. s etting rh0 to 00h will keep the pwm o u tp u t low. figure 13-5. 8 -bit asymmetric a l p u lse width mod u l a tion control inter r up t control inter r up t (8 bit s ) (8 bit s ) c/t = 0 c/t =1 t0 pin gate0 int0 pin tps tps clk sys clk sys ffh 00h rh0 (p3.4)t0 tf0 s et th0 time
84 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 13.6.1 mode 0 ? 8-bit pwm with 8-bit logarithmic prescaler in mode 0, tln a cts a s a log a rithmic presc a ler driving 8 -bit co u nter thn (see fig u re 13-6 ). the p s cn bits in tconb control the presc a ler v a l u e. on thn overflow, the d u ty cycle v a l u e in rhn is tr a nsferred to ocrn a nd the o u tp u t pin is set high. when the co u nt in thn m a tches ocrn, the o u tp u t pin is cle a red low. the following form u l a s give the o u tp u t freq u ency a nd d u ty cycle for timer n in pwm mode 0. timer 1 in pwm mode 0 is identic a l to timer 0. note: in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will h a lve the o u tp u t freq u ency. figure 13-6. timer/co u nter 1 pwm mode 0 13.6.2 mode 1 ? 8-bit pwm with 8-bit linear prescaler in mode 1, tln provides line a r presc a ling with a n 8 -bit au to-relo a d from rln (see fig u re 13-7 on p a ge 8 5 ). on tln overflow, tln is lo a ded with the v a l u e of rln. thn a cts a s a n 8 -bit co u nter. on thn overflow, the d u ty cycle v a l u e in rhn is tr a nsferred to ocrn a nd the o u tp u t pin is set high. when the co u nt in thn m a tches ocrn, the o u tp u t pin is cle a red low. the following form u - l a s give the o u tp u t freq u ency a nd d u ty cycle for timer n in pwm mode 1. timer 1 in pwm mode 1 is identic a l to timer 0. note: in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will h a lve the o u tp u t freq u ency. mode 0: f out f s y s 256 2 p s cn 1 + ---------------------------------------- - 1 tp s 1 + -------------------- - = d u ty cycle % 100 rhn 256 ----------- - = clk s y s tr1 gate1 int1 pin tl1 ( 8 bits) control p s c1 th1 ( 8 bits) ocr1 rh1 ( 8 bits) = t1 tp s mode 1: f out f s y s 256 256 rln ? () ------------------------------------------------ - 1 tp s 1 + -------------------- - = d u ty cycle % 100 rhn 256 ----------- - =
85 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 13-7. timer/co u nter 1 pwm mode 1 13.6.3 mode 2 ? 8-bit frequency generator timer n in pwm mode 2 f u nctions a s a n 8 -bit a u to-relo a d timer, the s a me a s norm a l mode 2, with the exception th a t the o u tp u t pin tn is toggled a t every tln overflow (see fig u re 13- 8 a nd fig u re 13-9 on p a ge 8 6 ). timer 1 in pwm mode 2 is identic a l to timer 0. pwm mode 2 c a n be u sed to o u tp u t a sq ua re w a ve of v a rying freq u ency. thn a cts a s a n 8 -bit co u nter. the following form u l a gives the o u tp u t freq u ency for timer n in pwm mode 2. note: in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will h a lve the o u tp u t freq u ency. figure 13-8. timer/co u nter 1 pwm mode 2 clk s y s tr1 gate1 int1 pin tl1 ( 8 bits) control th1 ( 8 bits) ocr1 rh1 ( 8 bits) = t1 rl1 ( 8 bits) tp s mode 2: f out f s y s 2256thn ? () ------------------------------------------ 1 tp s 1 + -------------------- - = clk s y s tr1 gate1 int1 pin tl1 ( 8 bits) control t1 th1 ( 8 bits) tp s
86 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 13-9. pwm mode 2 w a veform 13.6.4 mode 3 ? split 8-bit pwm timer 1 in pwm mode 3 simply holds its co u nt. the effect is the s a me a s setting tr1 = 0. timer 0 in pwm mode 3 est a blishes tl0 a nd th0 a s two sep a r a te pwm co u nters in a m a nner simil a r to norm a l mode 3. pwm mode 3 on timer 0 is shown in fig u re 13-10 . only the timer presc a ler is a v a il a ble to ch a nge the o u tp u t freq u ency d u ring pwm mode 3. tl0 c a n u se the timer 0 control bits: gate, tr0, int0 , pwm0en a nd tf0. th0 is locked into a timer f u nction a nd u ses tr1, pwm1en a nd tf1. rl0 provides the d u ty cycle for tl0 a nd rh0 provides the d u ty cycle for th0. pwm mode 3 is for a pplic a tions req u iring a single pwm ch a nnel a nd two timers, or two pwm ch a nnels a nd a n extr a timer or co u nter. with timer 0 in pwm mode 3, the at 8 9lp51rb2/rc2/ic2 c a n a ppe a r to h a ve fo u r timer/co u nters. when timer 0 is in pwm mode 3, timer 1 c a n be t u rned on a nd off by switching it o u t of a nd into its own mode 3. in this c a se, timer 1 c a n still be u sed by the seri a l port a s a b au d r a te gener a tor or in a ny a pplic a tion not req u iring a n interr u pt. the following form u l a s give the o u tp u t freq u ency a nd d u ty cycle for timer 0 in pwm mode 3. note: in f a st mode, tp s a pplies only when the tnx2 bits in ckcon0 a re set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting tnx2 in comp a tibility mode will h a lve the o u tp u t freq u ency. tx thx ffh mode 3: f out f s y s 256 ----------- 1 tp s 1 + -------------------- - = mode 3, t0: d u ty cycle % 100 rl0 256 ---------- - = mode 3, t1: d u ty cycle % 100 rh0 256 ----------- - =
87 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 13-10. timer/co u nter 0 pwm mode 3 14. timer 2 the at 8 9lp51rb2/rc2/ic2 incl u des a 16-bit timer/co u nter 2 with the following fe a t u res: ? 16-bit timer/co u nter with one 16-bit relo a d/c a pt u re register ? one extern a l relo a d/c a pt u re inp u t ? up/down co u nting mode with extern a l direction control ?uart b au d r a te gener a tion ?o u tp u t-pin toggle on timer overflow timer 2 is a 16-bit timer/co u nter th a t c a n oper a te a s either a timer or a n event co u nter. the type of oper a tion is selected by bit c/t2 in the s fr t2con. timer 2 h a s three oper a ting modes: c a pt u re, au to-relo a d ( u p or down co u nting), a nd b au d r a te gener a tor. the modes a re selected by bits in t2con a nd t2mod, a s shown in t a ble 14-1 . timer 2 consists of two 8 -bit registers, th2 a nd tl2. in the timer f u nction, the register is incre- mented every clock cycle. the timer r a te c a n be presc a led by a v a l u e between 1 a nd 16 u sing the timer presc a ler (see s ection 6.9 on p a ge 4 8 ). in comp a tibility mode the presc a ler is a lw a ys en a bled a nd tp s def au lts to 5, so timer 2 co u nts every six clock cycles (1/12 of the oscill a tor freq u ency in x1 mode or 1/6 of the oscill a tor freq u ency in x2 mode). in x2 mode timer 2 c a n be set to the x1 r a te by setting the t2x2 bit in ckcon1. in f a st mode the presc a ler is not en a bled by def au lt so the co u nt r a te is eq ua l to the system freq u ency (1/2 of the oscill a tor freq u ency in x1 mode or eq ua l to the oscill a tor freq u ency in x2 mode). in this c a se setting the t2x2 bit in ckcon1 en a bles the presc a ler for timer 2. note th a t timer 2 is not a ffected by the presc a ler when oper a ting in the b au d-r a te or freq u ency gener a tor modes. clk s y s tr0 gate0 int0 pin control tl0 ( 8 bits) ocr0 rl0 ( 8 bits) = t0 clk s y s th0 ( 8 bits) ocr1 rh0 ( 8 bits) = t1 tr1 tp s tp s
88 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: in f a st mode, tp s a pplies only when the t2x2 bit in ckcon0 is set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting t2x2 in comp a tibility mode will h a lve the timer freq u ency. in the co u nter f u nction, the register is incremented in response to a 1-to-0 tr a nsition a t its corre- sponding extern a l inp u t pin, t2. in f a st mode the extern a l inp u t is s a mpled every clock cycle. when the s a mples show a high in one cycle a nd a low in the next cycle, the co u nt is incre- mented. the new co u nt v a l u e a ppe a rs in the register d u ring the cycle following the one in which the tr a nsition w a s detected. s ince 2 clock cycles a re req u ired to recognize a 1-to-0 tr a nsition, the m a xim u m co u nt r a te is 1/2 of the system freq u ency. there a re no restrictions on the d u ty cycle of the inp u t sign a l, b u t it sho u ld be held for a t le a st one f u ll clock cycle to ens u re th a t a given level is s a mpled a t le a st once before it ch a nges. in comp a tibility mode the co u nter inp u t s a mpling is controlled by the presc a ler. s ince tp s def au lts to 6 in this mode, the pins a re s a mpled every six system clocks. therefore the inp u t sig- n a l sho u ld be held for a t le a st six clock cycles to ens u re th a t a given level is s a mpled a t le a st once before it ch a nges. the following definitions for timer 2 a re u sed in the s u bseq u ent p a r a gr a phs: table 14-1. timer 2 oper a ting modes rclk + tclk cp/rl2 dcen t2oe tr2 mode 0000116-bit a u to-relo a d 0010116-bit a u to-relo a d up-down 01x0116-bit c a pt u re 1 xxx1b au d r a te gener a tor xxx11freq u ency gener a tor x x x x 0 (off) table 14-2. timer 2 definitions symbol definition min 0000h max ffffh bottom 16-bit v a l u e of {rcap2h,rcap2l} f timer f s y s 2 t2x2 tp s 1 + () ----------------------------------------------- - = comp a tibility mode f timer f s y s tp s 1 + -------------------- - = f a st mode a nd t2x2 = 1 f timer f s y s = f a st mode a nd t2x2 = 0
89 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 14.1 timer 2 registers control a nd st a t u s bits for timer 2 a re cont a ined in registers t2con (see t a ble 14-3 ) a nd t2mod (see t a ble 14-4 ). the register p a ir {th2, tl2} a t a ddresses 0cdh a nd 0cch a re the 16-bit timer register for timer 2. the register p a ir {rcap2h, rcap2l} a t a ddresses 0cbh a nd 0cah a re the 16-bit c a pt u re/relo a d register for timer 2 in c a pt u re a nd au to-relo a d modes. note: the timer 2 oper a ting mode depends on bits in both t2con a nd t2mod a s shown in t a ble 14-1 . the rclk, tclk a nd t2oe bits h a ve priority over cp/rl2 . table 14-3. t2con ? timer/co u nter 2 control register t2con address = 0c 8 h reset v a l u e = 0000 0000b bit address a ble tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 bit76543210 symbol function tf2 timer 2 overflow flag s et by h a rdw a re when timer 2 overflows a nd m u st be cle a red by softw a re. tf2 will not be set when either rclk = 1 or tclk = 1. tf2 will gener a te a n interr u pt when et2 is set in ien0. exf2 timer 2 external flag s et when either a c a pt u re or relo a d is c au sed by a neg a tive tr a nsition on t2ex a nd exen2 = 1. when timer 2 interr u pt is en a bled, exf2 = 1 will c au se the cpu to vector to the timer 2 interr u pt ro u tine. exf2 m u st be cle a red by softw a re. exf2 does not c au se a n interr u pt in u p/down co u nter mode (dcen = 1) or d ua l-slope mode. rclk receive clock enable s et to u se timer 2 overflow p u lses for receive clock in seri a l port modes 1 a nd 3. cle a r to u se timer 1 overflows for the receive clock. tclk transmit clock enable s et to u se timer 2 overflow p u lses for tr a nsmit clock in seri a l port modes 1 a nd 3. cle a r to u se timer 1 overflows for the tr a nsmit clock. exen2 timer 2 external enable when set, a llows a c a pt u re or relo a d to occ u r a s a res u lt of a neg a tive tr a nsition on t2ex if timer 2 is not being u sed to clock the seri a l port. exen2 = 0 c au ses timer 2 to ignore events a t t2ex. tr2 timer 2 run control s t a rt/ s top control for timer 2. tr2 = 1 st a rts the timer. tr2 = 0 stops the timer. c/t2 timer/counter select 2 cle a r c/t2 = 0 for timer f u nction. s et c/t2 = 1 for extern a l event co u nter on t2 (p1.0) (f a lling edge triggered). c/t2 m u st be 0 to u se clock o u t mode. cp/rl2 capture/reload select cp/rl2 = 1 c au ses c a pt u res to occ u r on neg a tive tr a nsitions a t t2ex if exen2 = 1. cp/rl2 = 0 c au ses au tom a tic relo a ds to occ u r when timer 2 overflows or neg a tive tr a nsitions occ u r a t t2ex when exen2 = 1. when either rclk or tclk = 1, this bit is ignored a nd the timer is forced to au to-relo a d on timer 2 overflow.
90 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 14.2 capture mode in the c a pt u re mode, timer 2 is a fixed 16-bit timer or co u nter th a t co u nts u p from min to max. an overflow from max to min sets bit tf2 in t2con. if exen2 = 1, a 1-to-0 tr a nsition a t exter- n a l inp u t t2ex a lso c au ses the c u rrent v a l u e in th2 a nd tl2 to be c a pt u red into rcap2h a nd rcap2l, respectively. in a ddition, the tr a nsition a t t2ex c au ses bit exf2 in t2con to be set. the exf2 a nd tf2 bits c a n gener a te a n interr u pt. c a pt u re mode is ill u str a ted in fig u re 14-1 . the timer 2 overflow r a te in c a pt u re mode is given by the following eq ua tion: note: in f a st mode, tp s a pplies only when the t2x2 bit in ckcon0 is set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting t2x2 in comp a tibility mode will do u ble the timeo u t period. figure 14-1. timer 2 di a gr a m: c a pt u re mode table 14-4. t2mod ? timer 2 mode control register t2mod address = 0c9h reset v a l u e = 0000 0000b not bit address a ble ??????t2oedcen bit76543210 symbol function t2oe timer 2 output enable when t2oe = 1 a nd c/t 2 = 0, the t2 pin will toggle a fter every timer 2 overflow. dcen timer 2 down count enable when timer 2 oper a tes in a u to-relo a d mode a nd exen2 = 1, setting dcen = 1 will c au se timer 2 to co u nt u p or down depending on the st a te of t2ex. c a pt u re mode: time-o u t period 65536 f s y s ---------------- tp s 1 + () = tps exf2 t2ex pi n t2 pi n tr2 exen2 c/t2 = 0 c/t2 = 1 capture o verflo w transition detect or timer 2 interr upt rcap2h rcap2l tl2 th2 tf2 clk sys
91 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 14.3 auto-reload mode timer 2 c a n be progr a mmed to co u nt u p or down when config u red in its 16-bit au to-relo a d mode. this fe a t u re is invoked by the dcen (down co u nter en a ble) bit loc a ted in the s fr t2mod (see t a ble 14-4 ). upon reset, the dcen bit is set to 0 so th a t timer 2 will def au lt to co u nt u p. when dcen is set, timer 2 c a n co u nt u p or down, depending on the v a l u e of the t2ex pin. a s u mm a ry of the a u to-relo a d beh a viors is listed in t a ble 14-5 . 14.3.1 up counter fig u re 14-2 shows timer 2 au tom a tic a lly co u nting u p when dcen = 0. in this mode timer 2 co u nts u p to max a nd then sets the tf2 bit u pon overflow. the overflow a lso c au ses the timer registers to be relo a ded with bottom, the 16-bit v a l u e in rcap2h a nd rcap2l. if exen2 = 1, a 16-bit relo a d c a n be triggered either by a n overflow or by a 1-to-0 tr a nsition a t extern a l inp u t t2ex. this tr a nsition a lso sets the exf2 bit. both the tf2 a nd exf2 bits c a n gener a te a n inter- r u pt. the timer 2 overflow r a te for this mode is given in the following eq ua tion: note: in f a st mode, tp s a pplies only when the t2x2 bit in ckcon0 is set. tp s a lw a ys a pplies in comp a tibility mode, therefore setting t2x2 in comp a tibility mode will do u ble the timeo u t period. figure 14-2. timer 2 di a gr a m: a u to-relo a d mode (dcen = 0) table 14-5. su mm a ry of a u to-relo a d modes dcen t2ex direction behavior 0 x up relo a d to bottom 1 0 down u nderflow to max 1 1 up overflow to bottom bottom max u to-relo a d mode: dcen = 0 time-o u t period 65536 rcap2h rcap2l {,} ? f s y s ------------------------------------------------------------------------------ - tp s 1 + () = clk sys tl2 th2 tps
92 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 14-3. timer 2 w a veform: a u to-relo a d mode (dcen = 0) 14.3.2 up or down counter s etting dcen = 1 en a bles timer 2 to co u nt u p or down, a s shown in fig u re 14-5 . in this mode, the t2ex pin controls the direction of the co u nt (if exen2 = 1). a logic 1 a t t2ex m a kes timer 2 co u nt u p. when t2cm 1-0 = 00b, the timer will overflow a t max a nd set the tf2 bit. this overflow a lso c au ses bottom, the 16-bit v a l u e in rcap2h a nd rcap2l, to be relo a ded into the timer registers, th2 a nd tl2, respectively. a logic 0 a t t2ex m a kes timer 2 co u nt down. the timer u nderflows when th2 a nd tl2 eq ua l bottom, the 16-bit v a l u e stored in rcap2h a nd rcap2l. the u nderflow sets the tf2 bit a nd c au ses max to be relo a ded into the timer regis- ters. the exf2 bit toggles whenever timer 2 overflows or u nderflows a nd c a n be u sed a s a 17th bit of resol u tion. in this oper a ting mode, exf2 does not fl a g a n interr u pt. the beh a vior of timer 2 when dcen is en a bled is shown in fig u re 14-4 . the timer over- flow/ u nderflow r a te for u p-down co u nting mode is the s a me a s for u p co u nting mode, provided th a t the co u nt direction does not ch a nge. ch a nges to the co u nt direction m a y res u lt in longer or shorter periods between time-o u ts. figure 14-4. timer 2 w a veform: a u to-relo a d mode (dcen = 1) max min bottom tf2 s et max min bottom t2ex tf2 s et exf2
93 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 14-5. timer 2 di a gr a m: a u to-relo a d mode (dcen = 1) 14.4 baud rate generator timer 2 is selected a s the b au d r a te gener a tor by setting tclk a nd/or rclk in t2con ( t a ble 14-3 ). note th a t the b au d r a tes for tr a nsmit a nd receive c a n be different if timer 2 is u sed for the receiver or tr a nsmitter a nd timer 1 is u sed for the other f u nction. s etting rclk a nd/or tclk p u ts timer 2 into its b au d r a te gener a tor mode, a s shown in fig u re 14-6 . the b au d r a te gener a tor mode is simil a r to the au to-relo a d mode, in th a t a rollover in th2 c au ses the timer 2 registers to be relo a ded with the 16-bit v a l u e in registers rcap2h a nd rcap2l, which a re preset by softw a re. the b au d r a tes in uart modes 1 a nd 3 a re determined by timer 2?s overflow r a te a ccording to the following eq ua tion. the timer c a n be config u red for either timer or co u nter oper a tion. in most a pplic a tions, it is con- fig u red for timer oper a tion (cp/t2 = 0). the b au d r a te form u l a s a re given below. where (rcap2h, rcap2l) is the content of rcap2h a nd rcap2l t a ken a s a 16-bit u nsigned integer. timer 2 a s a b au d r a te gener a tor is shown in fig u re 14-6 . this fig u re is v a lid only if rclk or tclk = 1 in t2con. note th a t a rollover in th2 does not set tf2 a nd will not gener a te a n inter- r u pt. note too, th a t if exen2 is set, a 1-to-0 tr a nsition in t2ex will set exf2 b u t will not c au se a relo a d from (rcap2h, rcap2l) to (th2, tl2). th u s when timer 2 is in u se a s a b au d r a te gen- er a tor, t2ex c a n be u sed a s a n extr a extern a l interr u pt. also note th a t the b au d r a te a nd freq u ency gener a tor modes m a y be u sed sim u lt a neo u sly. tps clk sys modes 1 a nd 3 b au d r a tes timer 2 overflow r a te 16 ----------------------------------------------------------- - = modes 1, 3 b au d r a te f s y s 16 65536 rcap2h,rcap2l () ? [] ----------------------------------------------------------------------------------------------- =
94 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 14-6. timer 2 in b au d r a te gener a tor mode 14.5 frequency generator (p rogrammable clock out) timer 2 c a n gener a te a 50% d u ty cycle clock on t2 (p1.0). this pin, besides being a reg u l a r i/o pin, h a s two a ltern a te f u nctions. it c a n be progr a mmed to inp u t the extern a l clock for timer/co u nter 2 or to toggle its o u tp u t a t every timer overflow. to config u re the timer/co u nter 2 a s a clock gener a tor, bit c/t2 (t2con.1) m u st be cle a red a nd bit t2oe (t2mod.1) m u st be set. bit tr2 (t2con.2) st a rts a nd stops the timer. the clock-o u t freq u ency depends on the sys- tem freq u ency a nd the relo a d v a l u e of timer 2 c a pt u re registers (rcap2h, rcap2l), a s shown in the following eq ua tion. in the freq u ency gener a tor mode, timer 2 ro ll-overs will not gener a te a n interr u pt. this beh a vior is simil a r to when timer 2 is u sed a s a b au d-r a te gener a tor. it is possible to u se timer 2 a s a b au d-r a te gener a tor a nd a clock gener a tor sim u lt a neo u sly. note, however, th a t the b au d-r a te a nd clock-o u t freq u encies c a nnot be determined independently from one a nother since they both u se rcap2h a nd rcap2l. figure 14-7. timer 2 in clock-o u t mode smod1 rclk tclk rx clock tx clock t2ex pi n t2 pi n tr2 "1" "1" "1" "0" "0" "0" timer 1 overflow timer 2 interr upt 2 16 16 rcap2h rcap2l tl2 th2 c/t2 = 0 c/t2 = 1 exf2 transition detect or exen2 clk sys clock o u t freq u ency f s y s 2 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------- - = t2ex pin t2 pin tr2 timer 2 interrupt rcap2h rcap2l tl2 th2 c/t2 exf2 transition detector exen2 clk sys 2 t2oe
95 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 15. programmable counter array (pca) the pca provides more timing c a p a bilities with less cpu intervention th a n the st a nd a rd timer/co u nters. its a dv a nt a ges incl u de red u ced softw a re overhe a d a nd improved a cc u r a cy. the pca consists of a dedic a ted timer/co u nter which serves a s the time b a se for a n a rr a y of five comp a re/c a pt u re mod u les. its clock inp u t c a n be progr a mmed to co u nt a ny one of the following sign a ls: ? peripher a l clock freq u ency (f periph ) (tp s +1) ? peripher a l clock freq u ency (f periph ) 2 ? timer 0 overflow ? extern a l inp u t on eci (p1.2) e a ch comp a re/c a pt u re mod u le c a n be progr a mmed in a ny one of the following modes: ? rising a nd/or f a lling edge c a pt u re ? s oftw a re timer ? high-speed o u tp u t ?p u lse width mod u l a tor mod u le 4 c a n a lso be progr a mmed a s a w a tchdog timer (see ?pca w a tchdog timer? on p a ge 104 ). when the comp a re/c a pt u re mod u les a re progr a mmed in the c a pt u re mode, softw a re timer, or high speed o u tp u t mode, a n interr u pt c a n be gener a ted when the mod u le exec u tes its f u nction. all five mod u les pl u s the pca timer overflow sh a re one interr u pt vector. the pca timer/co u nter a nd comp a re/c a pt u re mod u les sh a re port 1 for extern a l i/o. these pins a re listed below. if one or sever a l bits in the port a re not u sed for the pca, they c a n still be u sed for st a nd a rd i/o. 15.1 pca timer/counter the pca timer is a common time b a se for a ll five mod u les (see fig u re 15-1 ). the timer co u nt so u rce is determined from the cp s 1 a nd cp s 0 bits in the cmod register ( t a ble 15-2 ) a nd c a n be progr a mmed to r u n a t: ? 1/6 the peripher a l clock freq u ency (f periph ) ? 1/2 the peripher a l clock freq u ency (f periph ) ? the timer 0 overflow ?the inp u t on the eci pin (p1.2) table 15-1. pca i/o pins pca component external i/o pin 16-bit co u nter p1.2/eci 16-bit mod u le 0 p1.3/cex0 16-bit mod u le 1 p1.4/cex1 16-bit mod u le 2 p1.5/cex2 16-bit mod u le 3 p1.6/cex3
96 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary the cmod register incl u des three a ddition a l bits a ssoci a ted with the pca ( s ee fig u re 15-1 a nd t a ble 15-2 ). ? the cidl bit which a llows the pca to stop d u ring idle mode. ? the wdte bit which en a bles or dis a bles the w a tchdog f u nction on mod u le 4. ( s ee fig u re 15- 4 a nd s ection 15.7 ) ? the ecf bit which when set c au ses a n interr u pt a nd the pca overflow fl a g cf (in the ccon s fr) to be set when the pca timer overflows. figure 15-1. pca timer/co u nter the ccon register cont a ins the r u n control bit for the pca a nd the fl a gs for the pca timer (cf) a nd e a ch mod u le (refer to t a ble 15-3 ). ? bit cr (ccon.6) m u st be set by softw a re to r u n the pca. the pca is sh u t off by cle a ring this bit. cl ch interr u pt ccapnl ccapnh 0 1 2 3 f periph (tp s +1) timer 0 overflow (p1.2) eci cr cf ecf cp s 1-0 f periph 2 idle cidl overflow to pca mod u les table 15-2. cmod ? pca co u nter mode register cmod address = 0d9h reset v a l u e = 00xx x000b not bit address a ble cidl wdte ? ? ? cp s 1cp s 0ecf bit76543210 symbol function cidl counter idle control cle a r to a llow the pca co u nter to f u nction d u ring idle mode. s et to h a lt the pca co u nter d u ring idle. wdte watchdog timer enable cle a r to dis a ble the w a tchdog timer f u nction on pca mod u le 4. s et to en a ble the w a tchdog f u nction of pca mod u le 4. cp s 1-0 pca count pulse select cp s 1 cp s 0 pca clock inp u t 00f periph /(tp s +1) *note: in f a st mode tp s is only a ctive when pcax2 = 1 in ckcon0. 01f periph /2 1 0 timer 0 overflow 11eci inp u t (p1.2) ecf pca enable counter overflow interrupt cle a r to prevent the cf bit in ccon from gener a ting a n interr u pt. s et to en a ble cf in ccon a s a n interr u pt so u rce.
97 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ? bit cf: the cf bit (ccon.7) is set when the pca co u nter overflows a nd a n interr u pt will be gener a ted if the ecf bit in the cmod register is set. the cf bit c a n only be cle a red by softw a re. ?bits 0 thro u gh 4 a re the fl a gs for the mod u les (bit 0 for mod u le 0, bit 1 for mod u le 1, etc.) a nd a re set by h a rdw a re when either a m a tch or a c a pt u re occ u rs. these fl a gs a lso c a n only be cle a red by softw a re. the pca interr u pt system is shown in fig u re 15-2 . table 15-3. ccon ? pca co u nter control register ccon address = 0d 8 h reset v a l u e = 00x0 0000b bit address a ble cf cr ? ccf4 ccf3 ccf2 ccf1 ccf0 bit76543210 symbol function cf pca counter overflow flag s et by h a rdw a re when the pca co u nter overflows from ffffh to 0000h. cf gener a tes a n interr u pt if the ecf bit in cmod a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. cr pca counter run control cle a r to dis a ble the pca co u nter from oper a ting. s et to en a ble the pca co u nter to co u nt a t the cp s r a te in cmod. ccf4 pca module 4 interrupt flag s et by h a rdw a re when a comp a re of m a tch occ u rs in mod u le 4. ccf4 gener a tes a n interr u pt if the eccf4 bit in ccapm4 a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. ccf3 pca module 3 interrupt flag s et by h a rdw a re when a comp a re of m a tch occ u rs in mod u le 2. ccf3 gener a tes a n interr u pt if the eccf3 bit in ccapm3 a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. ccf2 pca module 2 interrupt flag s et by h a rdw a re when a comp a re of m a tch occ u rs in mod u le 2. ccf2 gener a tes a n interr u pt if the eccf2 bit in ccapm2 a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. ccf1 pca module 1 interrupt flag s et by h a rdw a re when a comp a re of m a tch occ u rs in mod u le 1. ccf1 gener a tes a n interr u pt if the eccf1 bit in ccapm1 a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. ccf0 pca module 0 interrupt flag s et by h a rdw a re when a comp a re of m a tch occ u rs in mod u le 0. ccf0 gener a tes a n interr u pt if the eccf0 bit in ccapm0 a nd ec bit in ien0 a re both set. m u st be cle a red by softw a re. table 15-4. ch ? pca co u nter register high ch address = 0f9h reset v a l u e = 0000 0000b not bit address a ble c15 c14 c13 c12 c11 c10 c9 c 8 bit76543210 symbol function c 15- 8 module n compare/capture register high holds the higher order bits of the 16-bit pca timer/co u nter.
98 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 15-2. pca interr u pt s ystem 15.2 pca modules e a ch one of the five comp a re/c a pt u re mod u les h a s six possible f u nctions. it c a n perform: ? 16-bit c a pt u re, positive-edge triggered ? 16-bit c a pt u re, neg a tive-edge triggered ? 16-bit c a pt u re, both positive a nd neg a tive-edge triggered ? 16-bit s oftw a re timer ? 16-bit high s peed o u tp u t ? 8 -bit p u lse width mod u l a tor in a ddition, mod u le 4 c a n be u sed a s a w a tchdog timer. e a ch mod u le in the pca h a s a speci a l f u nction register a ssoci a ted with it. these registers a re: ccapm0 for mod u le 0, ccapm1 for mod u le 1, etc. ( s ee t a ble 15-6 ). the registers cont a in the bits th a t control the mode th a t e a ch mod u le will oper a te in. ? the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the mod u le) en a bles the ccf fl a g in the ccon s fr to gener a te a n interr u pt when a m a tch or comp a re occ u rs in the a ssoci a ted mod u le. ? pwm (ccapmn.1) en a bles the p u lse width mod u l a tion mode. table 15-5. cl ? pca co u nter register low cl address = 0e9h reset v a l u e = 0000 0000b not bit address a ble c7 c6 c5 c4 c3 c2 c1 c0 bit76543210 symbol function c 7-0 module n compare/capture register low holds the lower order bits of the 16-bit pca timer/co u nter. ec ea ccf0 ecf eccf0 eccf1 eccf2 eccf 3 eccf4 ccf0 ccf0 ccf0 ccf0 cf 0 1 2 3 4 7 ccon timer/counter module 4 module 3 module 2 module 1 module 0 ien0.6 ien0.7 pca interrupt to priority decoder cmod.0 ccapmn.0
99 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ? the tog bit (ccapmn.2) when set c au ses the cex o u tp u t a ssoci a ted with the mod u le to toggle when there is a m a tch between the pca co u nter a nd the mod u les c a pt u re/comp a re register. ?the m a tch bit mat (ccapmn.3) when set will c au se the ccfn bit in the ccon register to be set when there is a m a tch between the pca co u nter a nd the mod u les c a pt u re/comp a re register. ? the next two bits capn (ccapmn.4) a nd capp (ccapmn.5) de termine the edge th a t a c a pt u re inp u t will be a ctive on. the capn bit en a bles the neg a tive edge, a nd the capp bit en a bles the positive edge. if both bits a re set both edges will be en a bled a nd a c a pt u re will occ u r for either tr a nsition. ?the l a st bit in the register ecom (ccapmn.6) when set en a bles the comp a r a tor f u nction. t a ble 15-6 shows the ccapmn settings for the v a rio u s pca f u nctions. table 15-6. ccapmn ? pca mod u le n comp a re/c a pt u re control register (n = 0?4) ccapm0 address = 0dah reset v a l u e = x000 0000b ccapm1 address = 0dbh ccapm2 address = 0dch ccapm3 address = 0ddh ccapm4 address = 0deh not bit address a ble ? ecomn cappn capnn matn togn pwmn eccfn bit76543210 symbol function ecomn enable comparator cle a r to dis a ble the comp a r a tor f u nction of mod u le n. s et to en a ble the comp a r a tor f u nction of mod u le n cappn capture positive cle a r to dis a ble positive edge c a pt u re for mod u le n. s et to en a ble positive edge c a pt u re for mod u le n. capnn capture negative cle a r to dis a ble neg a tive edge c a pt u re for mod u le n. s et to en a ble neg a tive edge c a pt u re for mod u le n. matn match enable when matn = 1 a nd ecomn = 1 a m a tch between the pca co u nter a nd mod u le n?s comp a re/c a pt u re register will set the ccfn bit in ccon. cle a r matn to dis a ble setting of ccfn by comp a re events. togn toggle output when togn = 1 a nd ecomn = 1 a m a tch between the pca co u nter a nd mod u le n?s comp a re/c a pt u re register will toggle the cexn pin. cle a r togn to dis a ble toggling of cexn by comp a re events. pwmn pulse width modulation enable s et to config u re mod u le n in pwm mode a nd u se cexn a s a pwm o u tp u t. cle a r to dis a ble pwm mode for mod u le n. eccfn enable ccfn interrupt cle a r to dis a ble the ccfn bit in ccon a s a n interr u pt so u rce. s et to en a ble the ccfn bit in ccon to gener a te interr u pts.
100 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary there a re two a ddition a l registers a ssoci a ted with e a ch of the pca mod u les. they a re ccapnh a nd ccapnl a nd these a re the registers th a t store the 16-bit co u nt when a c a pt u re occ u rs or a comp a re sho u ld occ u r. when a mod u le is u sed in the pwm mode these registers a re u sed to control the d u ty cycle of the o u tp u t ( s ee t a ble 15-7 & t a ble 15- 8 ). note: pca mod u le modes (ccapmn registers ecomn cappn capnn matn togn pwmn eccfn module function 0000000no oper a tion x10000x16-bit c a pt u re by a positive-edge trigger on cexn x01000x16-bit c a pt u re by a neg a tive trigger on cexn x11000x16-bit c a pt u re by a tr a nsition on cexn 100100x16-bit s oftw a re timer/comp a re mode. 100110x16-bit high s peed o u tp u t 1000010 8 -bit pwm 1001x0xw a tchdog timer (mod u le 4 only) table 15-7. ccapnh ? pca mod u le n comp a re/c a pt u re register high (n = 0?4) ccap0h address = 0fah reset v a l u e = 0000 0000b ccap1h address = 0fbh ccap2h address = 0fch ccap3h address = 0fdh ccap4h address = 0feh not bit address a ble ccapn.15 ccapn.14 ccapn.13 ccapn.1 2 ccapn.11 ccapn.10 ccapn.9 ccapn. 8 bit76543210 symbol function ccapn 15- 8 module n compare/capture register high holds the higher order bits of the 16-bit comp a re/c a pt u re v a l u e for mod u le n. table 15-8. ccapnl ? pca mod u le n comp a re/c a pt u re register low (n = 0?4) ccap0l address = 0eah reset v a l u e = 0000 0000b ccap1l address = 0ebh ccap2l address = 0ech ccap3l address = 0edh ccap4l address = 0eeh not bit address a ble ccapn.7 ccapn.6 ccapn.5 ccapn.4 ccapn.3 ccapn.2 ccapn.1 ccapn.0 bit76543210 symbol function ccapn 7-0 module n compare/capture register low holds the lower order bits of the 16-bit comp a re/c a pt u re v a l u e for mod u le n.
101 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 15.3 pca capture mode to u se one of the pca mod u les in the c a pt u re mode either one or both of the ccapm bits capn a nd capp for th a t mod u le m u st be set. the extern a l cex inp u t for the mod u le (on port 1) is s a mpled for a tr a nsition. when a v a lid tr a nsition occ u rs the pca h a rdw a re lo a ds the v a l u e of the pca co u nter registers (ch a nd cl) into the mod u le's c a pt u re registers (ccapnl a nd cca- pnh). if the ccfn bit for the mod u le in the ccon s fr a nd the eccfn bit in the ccapmn s fr a re set then a n interr u pt will be gener a ted (refer to fig u re 15-3 ). figure 15-3. pca c a pt u re mode 15.4 16-bit software timer/ compare mode the pca mod u les c a n be u sed a s softw a re timers by setting both the ecom a nd mat bits in the mod u les ccapmn register. the pca timer will be comp a red to the mod u le's c a pt u re regis- ters a nd when a m a tch occ u rs a n interr u pt will occ u r if the ccfn (ccon s fr) a nd the eccfn (ccapmn s fr) bits for the mod u le a re both set ( s ee fig u re 15-4 ). figure 15-4. pca comp a re mode a nd pca w a tchdog timer before en a bling ecom bit, ccapnl a nd ccapnh sho u ld be set with a non zero v a l u e, other- wise a n u nw a nted m a tch co u ld h a ppen. writing to ccapnh will set the ecom bit. once ecom is set, writing ccapnl will cle a r ecom so th a t a n u nw a nted m a tch doesn?t occ u r while modify- ing the comp a re v a l u e. writing to ccapnh w ill set ecom. for this re a son, u ser softw a re sho u ld write ccapnl first, a nd then ccapnh. of co u rse, the ecom bit c a n still be controlled by a ccessing to ccapmn register. cl ch ccapnl ccapnh interr u pt cexn ccfn ccapmn.0 eccfn capnn ccapmn.4 cappn ccapmn.5 mod u le n cl ch ccapnl ccapnh interr u pt ccfn = matn ccapmn.3 ecomn 0 1 write to ccapnh write to ccapnl eccfn ccapmn.0 wdte cmod.6 (mod u le 4 only) mod u le n reset
102 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 15.5 high speed output mode in this mode the cex o u tp u t (on port 1) a ssoci a ted with the pca mod u le will toggle e a ch time a m a tch occ u rs between the pca co u nter a nd the mod u les c a pt u re registers a s shown in fig u re 15-6 . to a ctiv a te this mode the tog, mat, a nd ecom bits in the mod u le's ccapmn s fr m u st be set ( s ee fig u re 15-5 ). a prior write m u st be done to ccapnl a nd ccapnh before wr iting the ecomn bit. figure 15-5. pca high s peed o u tp u t mode before en a bling ecom bit, ccapnl a nd ccapnh sho u ld be set with a non zero v a l u e, other- wise a n u nw a nted m a tch co u ld h a ppen. once ecom is set, writing ccapnl will cle a r ecom so th a t a n u nw a nted m a tch doesn?t occ u r while modifying the comp a re v a l u e. writing to ccapnh will set ecom. for this re a son, u ser softw a re sho u ld write ccapnl first, a nd then ccapnh. of co u rse, the ecom bit c a n still be controlled by a ccessing to ccapmn register. an ex a mple of a high s peed o u tp u t w a veform is shown in fig u re 15-6 . the freq u ency of the o u tp u t c a n be controlled by relo a ding the pca timer in softw a re a nd/or ch a nging the comp a re v a l u es m u ltiple times per timeo u t period. figure 15-6. high s peed o u tp u t w a veform cl ch ccapnl ccapnh interr u pt ccfn = matn ccapmn.3 ecomn 0 1 write to ccapnh write to ccapnl eccfn ccapmn.0 togn ccapmn.2 mod u le n cexn {ch,cl} = ffffh togn = 1, ecomn = 1 cexn {ccapnh,ccapnl} {ch,cl} = 0000h
103 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 15.6 pulse width modulator mode all of the pca mod u les c a n be u sed a s pwm o u tp u ts. fig u re 15-7 shows the pwm f u nction. the freq u ency of the o u tp u t depends on the so u rce for the pca timer. all of the mod u les will h a ve the s a me freq u ency of o u tp u t bec au se they a ll sh a re the pca timer. the d u ty cycle of e a ch mod u le is independently v a ri a ble u sing the mod u les c a pt u re register ccapnl. when the v a l u e of the pca cl s fr is less th a n the v a l u e in the mod u les ccapnl s fr the o u tp u t will be low, when it is eq ua l to or gre a ter th a n the o u tp u t will be high. when cl overflows from ffh to 00h, ccapnl is relo a ded with the v a l u e in ccapnh. this a llows u pd a ting the pwm witho u t glitches. the pwm a nd ecom bits in the mod u le's ccapmn register m u st be set to en a ble the pwm mode. the following eq ua tions show the res u lting freq u ency a nd d u ty cycles of the gener a ted o u tp u t: figure 15-7. pca pwm mode an ex a mple pca pwm w a veform is shown in fig u re 15- 8 . figure 15-8. pca pwm w a veform cp s 00b: = f out f s y s 256 ----------- 1 tp s 1 + -------------------- - = d u ty cycle % 100 256 ccapnl ? 256 -------------------------------------- - = cl ccapnh ccapnl > ecomn pwmn ccapmn.1 mod u le n cexn + ? ecomn ccapmn.6 cl = ffh pwmn = 1, ecomn = 1 ccapnh cexn cl = 00h
104 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 15.7 pca watchdog timer an on-bo a rd w a tchdog timer is a v a il a ble with the pca to improve the reli a bility of the system witho u t incre a sing chip co u nt. w a tchdog timers a re u sef u l for systems th a t a re s u sceptible to noise, power glitches, or electrost a tic disch a rge. mod u le 4 is the only pca mod u le th a t c a n be progr a mmed a s a w a tchdog. however, this mod u le c a n still be u sed for other modes if the w a tchdog is not needed. fig u re 15-4 shows a di a gr a m of how the w a tchdog works. the u ser pre-lo a ds a 16-bit v a l u e in the comp a re registers. j u st like the other comp a re modes, this 16-bit v a l u e is comp a red to the pca timer v a l u e. if a m a tch is a llowed to occ u r, a n intern a l reset will be gener a ted. this reset will not c au se the r s t pin to be driven a ctive. in order to hold off the reset, the u ser h a s three options: 1. periodic a lly ch a nge the comp a re v a l u e so it will never m a tch the pca timer. 2. periodic a lly ch a nge the pca timer v a l u e so it will never m a tch the comp a re v a l u es. 3. dis a ble the w a tchdog by cle a ring the wdte bit before a m a tch occ u rs a nd then re- en a ble it. the first two options a re more reli a ble bec au se the w a tchdog timer is never dis a bled a s in option #3. if the progr a m co u nter ever goes a str a y, a m a tch will event ua lly occ u r a nd c au se a n intern a l reset. the second option is a lso not recommended if other pca mod u les a re being u sed. remember, the pca timer is the time b a se for a ll mod u les; ch a nging the time b a se for other mod u les wo u ld not be a good ide a . th u s, in most a pplic a tions the first sol u tion is the best option. this w a tchdog timer won?t gener a te a reset o u t on the reset pin. only the h a rdw a re w a tchdog c a n gener a te a bo a rd-level reset. 16. hardware watchdog timer the progr a mm a ble h a rdw a re w a tchdog timer (wdt) protects the system from incorrect exec u - tion by triggering a system reset when it times o u t a fter the softw a re h a s f a iled to feed the timer prior to the timer overflow. e a ch wdt clock cycle depends on the timer presc a ler (see s ection 6.9 on p a ge 4 8 ). by def au lt the wdt co u nts every 6 cpu clock cycles since tp s = 5. the pres- c a ler bits, p s 0, p s 1 a nd p s 2 in s fr wdtprg a re u sed to set the period of the w a tchdog timer from 16k to 204 8 k wdt clock cycles. the wdt is dis a bled by reset a nd d u ring power- down mode. when the wdt times o u t witho u t being serviced, a r s t p u lse l a st 96 system clocks (4 8 system clocks in x2 mode) is gener a ted to reset the cpu. this reset is a lso driven o u t on the r s t pin (see s ection 7.4 on p a ge 54 ) if the di s rto bit in wdtprg is not set. s ee t a ble 16-1 for the a v a il a ble wdt period selections the w a tchdog timer consists of a 14-bit timer with 7-bit progr a mm a ble presc a ler. writing the seq u ence 1eh/e1h to the wdtr s t register en a bles the timer. when the wdt is en a bled, the wdten bit in wdtprg will be set to ?1?. to prevent the wdt from gener a ting a reset when if overflows, the w a tchdog feed seq u ence m u st be written to wdtr s t before the end of the time- o u t period. to feed the w a tchdog, two write instr u ctions m u st be seq u enti a lly exec u ted s u ccess- f u lly. between the two write instr u ctions, s fr re a ds a re a llowed, b u t writes a re not a llowed. the instr u ctions sho u ld move 1eh to the wdtr s t register a nd then 1eh to the wdtr s t register. an incorrect feed or en a ble seq u ence will c au se a n immedi a te w a tchdog reset. time-o u t period 2 wto 14 + () f s y s ---------------------------- - tp s 1 + () =
105 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary the progr a m seq u ence to feed or en a ble the w a tchdog timer is a s follows: mov wdtr s t, #01eh mov wdtr s t, #0e1h the wdt time-o u t period is dependent on the system clock freq u ency. 16.1 software reset a s oftw a re reset of the at 8 9lp51rb2/rc2/ic2 is a ccomplished by writing the softw a re reset seq u ence 5ah/a5h to the wdtr s t s fr. the wdt does not need to be en a bled to gener a te the softw a re reset. a norm a l softw a re reset will set the s wr s t fl a g in wdtcon. however, if a t a ny time a n incorrect seq u ence is written to wdtr s t (i.e. a nything other th a n 1eh/e1h or 5ah/a5h), a softw a re reset will immedi a tely be gener a ted a nd both the s wr s t a nd wdtovf fl a gs will be set. in this m a nner a n intention a l softw a re reset m a y be disting u ished from a soft- w a re error-gener a ted reset. the progr a m seq u ence to gener a te a softw a re reset is a s follows: mov wdtr s t, #05ah mov wdtr s t, #0a5h a softw a re reset h a s the s a me d u r a tion a s the norm a l w a tchdog reset a nd will a lso gener a te a reset p u lse on the r s t pin u nless di s rto is set. table 16-1. w a tchdog timer time-o u t period s election wdt prescaler bits period () (clock cycles) ps2 ps1 ps0 000 16k x (tp s +1) 001 32k x (tp s +1) 010 64k x (tp s +1) 011 12 8 k x (tp s +1) 100 256k x (tp s +1) 101 512k x (tp s +1) 1 1 0 1024k x (tp s +1) 111 204 8 k x (tp s +1)
106 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 16.2 wdt registers ) table 16-2. wdtprg ? w a tchdog control register wdtprg address = a7h reset v a l u e = xx00 0000b not bit address a ble wdtovf s wr s twdtenwdidledi s rtowto2wto1wto0 bit76543210 symbol function wdtovf watchdog overflow flag s et by h a rdw a re when a wdt rest is gener a ted by the wdt timer overflow. also set when a n incorrect seq u ence is written to wdtr s t. m u st be cle a red by softw a re. s wr s t software reset flag s et by h a rdw a re when a softw a re reset is gener a ted by writing the seq u ence 5ah/a5h to wdtr s t. also set when a n incorrect seq u ence is written to wdtr s t. m u st be cle a red by softw a re. wdten watchdog enable flag this bit is read-only a nd reflects the st a t u s of the wdt (whether it is r u nning or not). the wdt is dis a bled a fter a ny reset a nd m u st be re-en a bled by writing 1eh/e1h to wdtr s t wdidle wdt disable during idle when wdidle = 0 the wdt contin u es to co u nt in idle mode. when wdidle = 1 the wdt h a lts co u nting in idle mode. di s rto disable reset output when di s tro = 0 the reset pin is driven to the s a me level a s pol when the wdt resets. when di s rto = 1 the reset pin is inp u t only. wto2 wto1 wto0 watchdog tiemout presc a ler bits for the w a tchdog timer (wdt). when a ll three bits a re cle a red to 0, the w a tchdog timer h a s a nomin a l period of 16k clock cycles. when a ll three bits a re set to 1, the nomin a l period is 204 8 k clock cycles. table 16-3. wdtr s t ? w a tchdog reset register wdtr s t address = a6h (write-only) not bit address a ble ???????? bit76543210 the wdt is en a bled by writing the seq u ence 1eh/e1h to the wdtr s t s fr. the c u rrent st a t u s m a y be checked by re a ding the wdten bit in wdtprg. to prevent th e wdt from resetting the device, the s a me seq u ence 1eh/e1h m u st be written to wdtr s t before the time-o u t interv a l expires. a softw a re reset is gener a ted by writing the seq u ence 5ah/a5h to wdtr s t.
107 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17. serial interface (uart) the seri a l interf a ce on the at 8 9lp51rb2/rc2/ic2 implements a univers a l asynchrono u s receiver/tr a nsmitter (uart). the uart h a s the following fe a t u res: ?f u ll-d u plex oper a tion ? 8 or 9 d a t a bits ?fr a ming error detection ?m u ltiprocessor comm u nic a tion mode with a u tom a tic address recognition ?b au d r a te gener a tor using timer 1, timer 2 or dedic a ted intern a l b au d r a te gener a tor ? interr u pt on receive b u ffer f u ll or tr a nsmission complete ? s ynchrono u s s pi or twi m a ster em u l a tion the seri a l interf a ce is f u ll-d u plex, which me a ns it c a n tr a nsmit a nd receive sim u lt a neo u sly. it is a lso receive-b u ffered, which me a ns it c a n begin receiving a second byte before a previo u sly received byte h a s been re a d from the receive register. (however, if the first byte still h a s not been re a d when reception of the second byte is complete, one of the bytes will be lost.) the seri a l port receive a nd tr a nsmit registers a re both a ccessed a t the s peci a l f u nction register s buf. writing to s buf lo a ds the tr a nsmit register, a nd re a ding s buf a ccesses a physic a lly sep a r a te receive register. the seri a l port c a n oper a te in the following fo u r modes. ? mode 0: s eri a l d a t a enters a nd exits thro u gh rxd. txd o u tp u ts the shift clock. eight d a t a bits a re tr a nsmitted/received, with the l s b first. the b au d r a te is progr a mm a ble to 1/6 or 1/3 the system freq u ency in comp a tibility mode, 1/4 or 1/2 the system freq u ency in f a st mode, or v a ri a ble b a sed on time 1. ? mode 1: 10 bits a re tr a nsmitted (thro u gh txd) or received (thro u gh rxd): a st a rt bit (0), 8 d a t a bits (l s b first), a nd a stop bit (1). on receive, the stop bit goes into rb 8 in the s peci a l f u nction register s con. the b au d r a te is v a ri a ble b a sed on timer 1 or timer 2. ? mode 2: 11 bits a re tr a nsmitted (thro u gh txd) or received (thro u gh rxd): a st a rt bit (0), 8 d a t a bits (l s b first), a progr a mm a ble 9th d a t a bit, a nd a stop bit (1). on tr a nsmit, the 9th d a t a bit (tb 8 in s con) c a n be a ssigned the v a l u e of ?0? or ?1?. for ex a mple, the p a rity bit (p, in the p s w) c a n be moved into tb 8 . on receive, the 9th d a t a bit goes into rb 8 in the s peci a l f u nction register s con, while the stop bit is ignored. the b au d r a te is progr a mm a ble to either 1/16 or 1/32 the system freq u ency. ? mode 3: 11 bits a re tr a nsmitted (thro u gh txd) or received (thro u gh rxd): a st a rt bit (0), 8 d a t a bits (l s b first), a progr a mm a ble 9th d a t a bit, a nd a stop bit (1). in f a ct, mode 3 is the s a me a s mode 2 in a ll respects except the b au d r a te, which is v a ri a ble b a sed on timer 1 or timer 2 in mode 3. in a ll fo u r modes, tr a nsmission is initi a ted by a ny instr u ction th a t u ses s buf a s a destin a tion register. reception is initi a ted in mode 0 by the condition ri = 0 a nd ren = 1. reception is initi- a ted in the other modes by the incoming st a rt bit if ren = 1.
108 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. s mod0 is loc a ted a t pcon.6. 2. f s y s = system freq u ency. the b au d r a te depends on s mod1 (pcon.7). table 17-1. s con ? s eri a l port control register s con address = 9 8 h reset v a l u e = 0000 0000b bit address a ble s m0/fe s m1 s m2 ren tb 8 rb 8 t1 ri bit7 6543210 ( s mod0 = 0/1) (1) symbol function fe framing error bi t this bit is set by the receiver when a n inv a lid stop bit is detected. the fe bit is not cle a red by v a lid fr a mes a nd m u st be cle a red by softw a re. the s mod0 bit m u st be set to en a ble a ccess to the fe bit. fe will be set reg a rdless of the st a te of s mod0. s m0 serial port mode bit 0 refer to s m1 for seri a l port mode selection. s mod0 m u st = 0 to a ccess bit s m0. s m1 serial port mode bit 1 s m2 multiprocessor communications enable en a bles the a u tom a tic address recognition fe a t u re in modes 2 or 3. if s m2 = 1 then rl will not be set u nless the received 9th d a t a bit (rb 8 ) is 1, indic a ting a n a ddress, a nd the received byte is a given or bro a dc a st address. in mode 1, if s m2 = 1 then rl will not be a ctiv a ted u nless a v a lid stop bit w a s received, a nd the received byte is a given or bro a dc a st address. in mode 0, s m2 determines the idle st a te of the shift clock s u ch th a t the clock is the inverse of s m2, i.e. when s m2 = 0 the clock idles high a nd when s m2 = 1 the clock idles low. ren serial reception enable s et by softw a re to en a ble reception. cle a r by softw a re to dis a ble reception. tb 8 transmitter bit 8 the 9th d a t a bit th a t will be tr a nsmitted in modes 2 a nd 3. s et or cle a r by softw a re a s desired. in mode 0, setting tb 8 en a bles timer 1 a s the shift clock gener a tor. rb 8 receiver bit 8 in modes 2 a nd 3, the 9th d a t a bit th a t w a s received. in mode 1, if s m2 = 0, rb 8 is the stop bit th a t w a s received. in mode 0, rb 8 is not u sed. ti transmit interrupt flag s et by h a rdw a re a t the end of the 8 th bit time in mode 0, or a t the beginning of the stop bit in the other modes, in a ny seri a l tr a nsmission. m u st be cle a red by softw a re. ri receive interrupt flag s et by h a rdw a re a t the end of the 8 th bit time in mode 0, or h a lfw a y thro u gh the stop bit time in the other modes, in a ny seri a l reception (except see s m2). m u st be cle a red by softw a re. sm0 sm1 mode description baud rate (compat.) (2) baud rate (fast) (2) 0 0 0 shift register f s y s /3 or f s y s /6 or timer 1 f s y s /2 or f s y s /4 or timer 1 011 8 -bit uart v a ri a ble (timer 1 or timer 2) v a ri a ble (timer 1 or timer 2) 1 0 2 9-bit uart f s y s /32 or f s y s /16 f s y s /32 or f s y s /16 1 1 3 9-bit uart v a ri a ble (timer 1 or timer 2) v a ri a ble (timer 1 or timer 2)
109 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.1 multiprocessor communications modes 2 a nd 3 h a ve a speci a l provision for m u ltiprocessor comm u nic a tions. in these modes, 9d a t a bits a re received, followed by a stop bit. the 9th bit goes into rb 8 . then comes a stop bit. the port c a n be progr a mmed s u ch th a t when the stop bit is received, the seri a l port interr u pt is a ctiv a ted only if rb 8 = 1. this fe a t u re is en a bled by setting bit s m2 in s con. the following ex a mple shows how to u se the seri a l interr u pt for m u ltiprocessor comm u nic a tions. when the m a ster processor m u st tr a nsmit a block of d a t a to one of sever a l sl a ves, it first sends o u t a n a ddress byte th a t identifies the t a rget sl a ve. an a ddress byte differs from a d a t a byte in th a t the 9th bit is ?1? in a n a ddress byte a nd ?0? in a d a t a byte. with s m2 = 1, no sl a ve is interr u pted by a d a t a byte. an a ddress byte, however, interr u pts a ll sl a ves. e a ch sl a ve c a n ex a mine the received byte a nd see if it is being a ddressed. the a ddressed sl a ve cle a rs its s m2 bit a nd prep a res to receive the d a t a bytes th a t follows. the sl a ves th a t a re not a ddressed set their s m2 bits a nd ignore the d a t a bytes. s ee ?a u tom a tic address recognition? on p a ge 114. the s m2 bit c a n be u sed to check the v a lidity of the stop bit in mode 1. in a mode 1 reception, if s m2 = 1, the receive interr u pt is not a ctiv a ted u nless a v a lid stop bit is received. 17.2 baud rates the b au d r a te in mode 0 depends on the v a l u e of the s mod1 bit in s peci a l f u nction register pcon.7. if s mod1 = 0 (the v a l u e on reset) a nd tb 8 =0, the b au d r a te is 1/4 of the system fre- q u ency in f a st mode. if s mod1 = 1 a nd tb 8 = 0, the b au d r a te is 1/2 of the system freq u ency, a s shown in the following eq ua tion: in comp a tibility mode the b au d r a te is 1/6 of the system freq u ency, sc a ling to 1/3 when s mod1 = 1. mode 0 c a n a lso be gener a ted from either timer 1 or the intern a l b au d r a te gener a tor by setting tb 8 in s con or s rc in bdrcon respectively. the b au d r a te in mode 2 a lso depends on the v a l u e of the s mod1 bit. if s mod1 = 0, the b au d r a te is 1/32 of the system freq u ency. if s mod1 = 1, the b au d r a te is 1/16 of the system fre- q u ency, a s shown in the following eq ua tion: the b au d r a te in modes 1 a nd 3 is gener a ted from one of timer 1, timer 2 or the intern a l b au d r a te gener a tor a s det a iled in t a ble 17-2 . mode 0 b au d r a te tb 8 = 0 2 s mod1 4 -------------------- s ystem freq u ency = mode 0 b au d r a te tb 8 = 0 2 s mod1 6 -------------------- s ystem freq u ency = mode 2 b au d r a te 2 s mod1 32 -------------------- s ystem freq u ency =
110 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.2.1 using timer 1 to generate baud rates s etting tb 8 = 1 in mode 0 en a bles timer 1 a s the b au d r a te gener a tor. when timer 1 is the b au d r a te gener a tor for mode 0, the b au d r a tes a re determined by the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: the timer 1 overflow r a te norm a lly determines the b au d r a tes in modes 1 a nd 3. when timer 1 is the b au d r a te gener a tor, the b au d r a tes a re determined by the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: the timer 1 interr u pt sho u ld be dis a bled in this a pplic a tion. the timer itself c a n be config u red for either timer or co u nter oper a tion in a ny of its 3 r u nning modes. in the most typic a l a pplic a - tions, it is config u red for timer oper a tion in au to-relo a d mode (high nibble of tmod = 0010b). in this c a se, the b au d r a te is given by the following form u l a : t a ble 17-3 lists commonly u sed b au d r a tes a nd how they c a n be obt a ined from timer 1. table 17-2. uart b au d r a te s election t a ble for modes 1 a nd 3 tclk (t2con.4) rclk (t2con.5) tbck (bdrcon.3) rbck (bdrcon.2) clock source uart tx clock source uart rx 0 0 0 0 timer 1 timer 1 1 0 0 0 timer 2 timer 1 0 1 0 0 timer 1 timer 2 1 1 0 0 timer 2 timer 2 x010brgtimer 1 x110brgtimer 2 0 x 0 1 timer 1 brg 1 x 0 1 timer 2 brg xx1 1brgbrg mode 0 b au d r a te tb 8 = 1 2 s mod1 4 -------------------- (timer 1 overflow r a te) = modes 1, 3 b au d r a te 2 s mod1 32 -------------------- (timer 1 overflow r a te) = modes 1, 3 b au d r a te 2 s mod1 32 -------------------- s ystem freq u ency 256 th1 () ? [] ------------------------------------------------- - 1 tp s 1 + -------------------- - =
111 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.2.2 using timer 2 to generate baud rates timer 2 is selected a s the b au d r a te gener a tor by setting tclk a nd/or rclk in t2con. under these conditions, the b au d r a tes for tr a nsmit a nd receive c a n be sim u lt a neo u sly different by u sing timer 1 for tr a nsmit a nd timer 2 for receive, or vice vers a . the b au d r a te gener a tor mode is simil a r to the au to-relo a d mode, in th a t a rollover c au ses the timer 2 registers to be relo a ded with the 16-bit v a l u e in registers rcap2h a nd rcap2l, which a re preset by softw a re. in this c a se, the b au d r a tes in modes 1 a nd 3 a re determined by timer 2?s overflow r a te a ccording to the following eq ua tion: t a ble 17-4 lists commonly u sed b au d r a tes a nd how they c a n be obt a ined from timer 2. note th a t tp s a nd t2x2 do not a pply to timer 2 in b au d r a te mode. table 17-3. commonly used b au d r a tes gener a ted by timer 1 baud rate f osc (mhz) x2 smod1 timer 1 c/t mode tps reload value mode 0 m a x: 6 mhz 12 1 1 x x 0 x mode 2 m a x: 750k 12 1 1 x x 0 x modes 1, 3 m a x: 750k 12 1 1 0 2 0 f4h 19.2k 11.059 1 1 0 2 0 dch 9.6k 11.059 1 0 0 2 0 dch 4. 8 k 11.05910020 b 8 h 2.4k 11.059 1 0 0 2 0 70h 1.2k 11.059 1 0 0 1 0 fee0h 137.5 11.9 8 610010f55ch 110 6 1 1 0 1 0 f2afh 110 1210010f2afh 19.2k 11.059 0 1 0 2 5 fdh 9.6k 11.059 0 0 0 2 5 fdh 4. 8 k 11.05900025 fah 2.4k 11.059 0 0 0 2 5 f4h 1.2k 11.059 0 0 0 2 5 e 8 h 137.5 11.9 8 600025 1dh 110 6 0 0 0 2 5 72h 110 12 0 0 0 1 5 feebh modes 1 a nd 3 b au d r a te 1 16 ------ s ystem freq u ency 65536 rcap2h,rcap2l () ? [] --------------------------------------------------------------------------------- =
112 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.2.3 internal baud rate generator (brg) the at 8 9lp51rb2/rc2/ic2 incl u des a n intern a l b au d r a te gener a tor (brg) for uart modes 1 a nd 3 th a t c a n free u p timer 1 or timer 2 for other u ses. the brg is a n 8 -bit co u nter with relo a d a s shown in fig u re 17-1 . on overflow, the brg is lo a ded with the v a l u e of brl. the brg is controlled by the bdrcon register ( s ee t a ble 17-7 ). the brg oper a tes when brr = 1. the s pd bit determines the clock so u rce: either the system clock di vided-by-6 or the system clock with no division. the brg is not a ffected by the timer presc a ler; however, it is a ffected by the s mod1 bit in pcon. the following eq ua tion shows the b au d r a te c a lc u l a tion u sing the brg: the o u tp u t of the intern a l b au d r a te gener a tor c a n be independently selected for the tr a nsmit a nd receive clocks u sing the tbck a nd rbck bits in bdrcon. these bits h a ve priority over the tclk a nd tclk bits in t2con a s shown in t a ble 17-2 . t a ble 17-5 lists some common b au d r a tes gener a ted by the brg. table 17-4. commonly used b au d r a tes gener a ted by timer 2 baud rate f osc (mhz) x2 timer 2 cp/rl2 c/t2 tclk or rclk reload value m a x: 750k 12 1 0 0 1 ffffh 19.2k 11.059 1 0 0 1 ffdch 9.6k 11.059 1 0 0 1 ffb 8 h 4. 8 k 11.059 1 0 0 1 ff70h 2.4k 11.059 1 0 0 1 fee0h 1.2k 11.059 1 0 0 1 fdc0h 137.5 11.9 8 61 0 0 1 eab 8 h 110 6 1 0 0 1 f2afh 110 12 1 0 0 1 e55eh 19.2k 11.059 0 0 0 1 ffeeh 9.6k 11.059 0 0 0 1 ffdch 4. 8 k 11.059 0 0 0 1 ffb 8 h 2.4k 11.059 0 0 0 1 ff70h 1.2k 11.059 0 0 0 1 fee0h 137.5 11.9 8 6 0 0 0 1 f55ch 110 12 0 0 0 1 f2afh b au d r a te 2 s mod1 32 -------------------- f s y s 256 brl () ? -------------------------------- 1 6 1 s pd ? () ------------------------ =
113 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-1. intern a l b au d r a te gener a tor table 17-5. commonly used b au d r a tes gener a ted by brg baud rate x2 smod1 spd f osc = 16.384 mhz f osc = 24 mhz brl error (%) brl error (%) 115200 1 1 1 247 1.23 243 0.16 57600 1 1 1 23 8 1.23 230 0.16 3 8 400 1 1 1 229 1.23 217 0.16 2 88 00 1 1 1 220 1.23 204 0.16 19200 1 1 1 203 0.63 17 8 0.16 9600 1 1 1 149 0.31 100 0.16 4 8 00 1 1 1 43 1.23 ? ? 4 8 00 0 0 0 247 1.23 243 0.16 2400 0 0 0 23 8 1.23 230 0.16 1200 0 0 0 220 1.23 202 3.55 600 0 0 0 1 8 50.161520.16 brg brl uart 0 1 brr (bdrcon.4) clk s y s overflow s pd (bdrcon.1) 6 0 1 s mod1 (pcon.7) 6 table 17-6. brl ? b au d r a te relo a d register brl address = 09ah reset v a l u e = 0000 0000b not bit address a ble bit76543210 symbol function brl 7-0 baud rate reload value holds the 8 -bit relo a d v a l u e of the intern a l b au d r a te gener a tor. this v a l u e is lo a ded into the brg when the brg overflows from ffh to 00h.
114 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.3 framing error detection in a ddition to a ll of its u s ua l modes, the uart c a n perform fr a ming error detection by looking for missing stop bits. when u sed for fr a ming error detect, the uart l ooks for missing stop bits in the comm u nic a tion. a missing bit will set the fe bit in the s con register. the fe bit sh a res the s con.7 bit with s m0 a nd the f u nction of s con.7 is determined by pcon.6 ( s mod0). if s mod0 is set then s con.7 f u nctions a s fe. s con.7 f u nctions a s s m0 when s mod0 is cle a red. when u sed a s fe, s con.7 c a n only be cle a red by softw a re. the fe bit will be set by a fr a ming error reg a rdless of the st a te of s mod0. 17.4 automatic ad dress recognition a u tom a tic address recognition is a fe a t u re which a llows the uart to recognize cert a in a ddresses in the seri a l bit stre a m by u sing h a rdw a re to m a ke the comp a risons. this fe a t u re s a ves a gre a t de a l of softw a re overhe a d by elimin a ting the need for the softw a re to ex a mine every seri a l a ddress which p a sses by the seri a l port. this fe a t u re is en a bled by setting the s m2 bit in s con for modes 1, 2 or 3. in the 9-bit uart modes, mode 2 a nd mode 3, the receive interr u pt fl a g (ri) will be au tom a tic a lly set when the received byte cont a ins either the ?given? a ddress or the ?bro a dc a st? a ddress. the 9-bit mode req u ires th a t the 9th inform a tion bit be a ?1? to indic a te th a t the received inform a tion is a n a ddress a nd not d a t a . in mode 1 ( 8 -bit) the ri fl a g will be set if s m2 is en a bled a nd the inform a tion received h a s a v a lid stop bit following the 8 th a ddress bits a nd the inform a tion is either a given or bro a dc a st a ddress. using the a u tom a tic address recognition fe a t u re a llows a m a ster to selectively com- m u nic a te with one or more sl a ves by invoking the given sl a ve a ddress or a ddresses. all of the sl a ves m a y be cont a cted by u sing the bro a dc a st a ddress. a u tom a tic address recognition is not a v a il a ble d u ring mode 0. table 17-7. bdrcon ? b au d r a te control register bdrcon address = 9bh reset v a l u e = xxx0 0000b not bit address a ble ? ? ? brr tbck rbck s pd s rc bit76543210 symbol function brr baud rate run control cle a r to stop the intern a l b au d r a te gener a tor. s et to st a rt the intern a l b au d r a te gener a tor. tbck transmission baud rate select cle a r to select timer 1 or timer 2 overflow a s tr a nsmit clock for the seri a l port. s et to select the intern a l b au d r a te gener a tor a s tr a nsmit clock for the seri a l port. rbck receive baud rate select cle a r to select timer 1 or timer 2 overflow a s receive clock for the seri a l port. s et to select the intern a l b au d r a te gener a tor a s receive clock for the seri a l port. s pd brg speed control cle a r to select the s low b au d r a te gener a tor mode. s et to select the fa s t b au d r a te gener a tor mode. s rc baud rate source for mod e 0 cle a r to select fixed or timer 1 clock so u rce for uart mode 0. s et to select brg for uart mode 0.
115 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.4.1 given address two speci a l f u nction registers a re u sed to define the sl a ve?s a ddress, s addr (a9h), a nd the a ddress m a sk, s aden (b9h). s aden is u sed to define which bits in the s addr a re to be u sed a nd which bits a re ?don?t c a re?. the s aden m a sk c a n be logic a lly anded with the s addr to cre a te the ?given? a ddress which the m a ster will u se for a ddressing e a ch of the sl a ves. use of the given a ddress a llows m u ltiple sl a ves to be recognized while excl u ding others. the following ex a mples show the vers a tility of this scheme: s l a ve 0 s addr = 1100 0000 s aden = 1111 1101 given = 1100 00x0 s l a ve 1 s addr = 1100 0000 s aden = 1111 1110 given = 1100 000x in the previo u s ex a mple, s addr is the s a me a nd the s aden d a t a is u sed to differenti a te between the two sl a ves. s l a ve 0 req u ires a ?0? in bit 0 a nd it ignores bit 1. s l a ve 1 req u ires a ?0? in bit 1 a nd bit 0 is ignored. a u niq u e a ddress for sl a ve 0 wo u ld be 1100 0010 since sl a ve 1 req u ires a ?0? in bit 1. a u niq u e a ddress for sl a ve 1 wo u ld be 1100 0001 since a ?1? in bit 0 will excl u de sl a ve 0. both sl a ves c a n be selected a t the s a me time by a n a ddress which h a s bit 0 = 0 (for sl a ve 0) a nd bit 1 = 0 (for sl a ve 1). th u s, both co u ld be a ddressed with 1100 0000. in a more complex syst em, the following co u ld be u sed to select sl a ves 1 a nd 2 while excl u ding sl a ve 0: s l a ve 0 s addr = 1100 0000 s aden = 1111 1001 given = 1100 0xx0 s l a ve 1 s addr = 1110 0000 s aden = 1111 1010 given = 1110 0x0x s l a ve 2 s addr = 1110 0000 s aden = 1111 1100 given = 1110 00xx in the a bove ex a mple, the differenti a tion a mong the 3 sl a ves is in the lower 3 a ddress bits. s l a ve 0 req u ires th a t bit 0 = 0 a nd it c a n be u niq u ely a ddressed by 1110 0110. s l a ve 1 req u ires th a t bit 1 = 0 a nd it c a n be u niq u ely a ddressed by 1110 a nd 0101. s l a ve 2 req u ires th a t bit 2 = 0 a nd its u niq u e a ddress is 1110 0011. to select s l a ves 0 a nd 1 a nd excl u de s l a ve 2, u se a ddress 1110 0100, since it is necess a ry to m a ke bit 2 = 1 to excl u de sl a ve 2. upon reset the s addr a nd s aden registers a re lo a ded with ?0?s. this prod u ces a given a ddress of a ll ?don?t c a res? a s well a s a bro a dc a st a ddress of a ll ?don?t c a res?. this effectively dis a bles the a u tom a tic addressing mode a nd a llows the microcontroller to u se st a nd a rd 8 0c51- type uart drivers which do not m a ke u se of this fe a t u re.
116 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.4.2 broadcast address the bro a dc a st address for e a ch sl a ve is cre a ted by t a king the logic or of s addr a nd s aden. zeros in this res u lt a re trended a s don?t c a res. in most c a ses, interpreting the don?t c a res a s ones, the bro a dc a st a ddress will be ff hex a decim a l. 17.5 more about mode 0 in mode 0, the uart is config u red a s a two wire h a lf-d u plex synchrono u s seri a l interf a ce. in two-wire mode seri a l d a t a enters a nd exits thro u gh rxd a nd txd o u tp u ts the shift clock. eight d a t a bits a re tr a nsmitted/received, with the l s b first. fig u re 17-4 a nd fig u re 17.6 on p a ge 120 show simplified f u nction a l di a gr a ms of the seri a l port in mode 0 a nd a ssoci a ted timing. the b au d r a te is progr a mm a ble to 1/2 or 1/4 the system freq u ency by setting/cle a ring the s mod1 bit in f a st mode, or 1/3 or 1/6 the system freq u ency in comp a tibility mode. however, ch a nging s mod1 h a s a n effect on the rel a tionship between the clock a nd d a t a a s described below. the b au d r a te c a n a lso be gener a ted by timer 1 by setting tb 8 in s con or the intern a l b au d r a te gener a tor by setting s rc in bdrcon. t a ble 17-10 lists the b au d r a te options for mode 0. table 17-8. s addr ? s l a ve address register s addr address = 0a9h reset v a l u e = 0000 0000b not bit address a ble bit76543210 symbol function s addr 7-0 uart slave address when s m2 = 1, s addr holds the 8 -bit a ddress for the uart m u ltiprocessor comm u nic a tion mode. this a ddress is combined with s aden to cre a te the given a nd bro a dc a st a ddresses for the device. table 17-9. s aden ? s l a ve address m a sk register s aden address = 0b9h reset v a l u e = 0000 0000b not bit address a ble bit76543210 symbol function s aden 7-0 uart slave address mask when s m2 = 1, s aden holds the 8 -bit a ddress m a sk for the uart m u ltiprocessor comm u nic a tion mode. this a ddress is combined with s addr to cre a te the given a nd bro a dc a st a ddresses for the device. table 17-10. mode 0 b au d r a tes src tb8 smod1 baud rate (fast) baud rate (compatibility) 000 f s y s /4 f s y s /6 001 f s y s /2 f s y s /3 0 1 0 (timer 1 overflow) / 4 (timer 1 overflow) / 4 0 1 1 (timer 1 overflow) / 2 (timer 1 overflow) / 2 1 x 0 (brg overflow) / 2 (brg overflow) / 2 1 x 1 brg overflow brg overflow
117 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.5.1 two-wire (half-duplex) mode tr a nsmission is initi a ted by a ny instr u ction th a t u ses s buf a s a destin a tion register. the ?write to s buf? sign a l a lso lo a ds a ?1? into the 9th position of the tr a nsmit shift register a nd tells the tx control block to begin a tr a nsmission. the intern a l timing is s u ch th a t one f u ll bit slot m a y el a pse between ?write to s buf? a nd a ctiv a tion of s end. s end tr a nsfers the o u tp u t of the shift register to the a ltern a te o u tp u t f u nction line of p3.0, a nd a lso tr a nsfers s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. as d a t a bits shift o u t to the right, ?0?s come in from the left. when the m s b of the d a t a byte is a t the o u tp u t position of the shift register, the ?1? th a t w a s initi a lly lo a ded into the 9th position is j u st to the left of the m s b, a nd a ll positions to the left of th a t cont a in ?0?s. this condition fl a gs the tx control block to do one l a st shift, then de a ctiv a te s end a nd set ti. reception is initi a ted by the condition ren = 1 a nd ri = 0. at the next clock cycle, the rx con- trol u nit writes the bits 11111110b to the receive shift register a nd a ctiv a tes receive in the next clock ph a se. receive en a bles s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. as d a t a bits come in from the right, ?1?s shift o u t to the left. when the ?0? th a t w a s initi a lly lo a ded into the right-most position a rrives a t the left-most position in the shift register, it fl a gs the rx control block to do one l a st shift a nd lo a d s buf. then receive is cle a red a nd ri is set. the rel a tionship between the shift clock a nd d a t a is determined by the combin a tion of the s m2 a nd s mod1 bits a s listed in t a ble 17-11 a nd shown in fig u re . the s m2 bit determines the idle st a te of the clock when not c u rrently tr a nsmitting/receiving. the s mod1 bit determines if the o u tp u t d a t a is st a ble for both edges of the clock, or j u st one. in two-wire config u r a tion mode 0 m a y be u sed a s a h a rdw a re a cceler a tor for softw a re em u l a - tion of seri a l interf a ces s u ch a s a h a lf-d u plex s eri a l peripher a l interf a ce ( s pi) m a ster in mode (0,0) or (1,1) or a two-wire interf a ce (twi) in m a ster mode. an ex a mple of mode 0 em u l a ting a twi m a ster device is shown in fig u re 17-3 . in this ex a mple, the st a rt, stop, a nd a cknowledge a re h a ndled in softw a re while the byte tr a nsmission is done in h a rdw a re. f a lling/rising edges on txd a re cre a ted by setting/cle a ring s m2. rising/f a lling edges on rxd a re forced by set- ting/cle a ring the p3.0 register bit. s m2 a nd p3.0 m u st be 1 while the byte is being tr a nsferred. mode 0 tr a nsfers d a t a l s b first where a s s pi or twi a re gener a lly m s b first. em u l a tion of these interf a ces m a y req u ire bit revers a l of the tr a nsferred d a t a bytes. the following code ex a mple reverses the bits in the a cc u m u l a tor: ex: mov r7, #8 revrs: rlc a ; c << msb (acc) xch a, r6 rrc a ; msb (acc) >> b xch a, r6 djnz r7, revrs table 17-11. mode 0 clock a nd d a t a modes sm2 smod1 clock idle data changes data sampled 0 0 high while clock is high positive edge of clock 0 1 high neg a tive edge of clock positive edge of clock 1 0 low while clock is low neg a tive edge of clock 1 1 low neg a tive edge of clock positive edge of clock
118 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-2. mode 0 w a veforms (two-wire) figure 17-3. uart mode 0 twi em u l a tion ( s mod1 = 1) 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 s mod1 = 0 s m2 = 0 s mod1 = 1 s m2 = 0 s mod1 = 0 s m2 = 1 s mod1 = 1 s m2 = 1 7 ( s da) rxd ( s cl) txd 6 5 4 3 2 1 0 ack s m2 p3.0 write to s buf ti sa mple ack
119 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-4. s eri a l port mode 0 (two-wire) internal b u s f sys internal b u s txd ( s hift clock) rxd ( d a t a out ) txd ( s hift clock) rxd ( d a t a in ) write t o s b u f s end s hift ti write t o s con (clear ri ) s hift receive ri ?1? 2 tb 8 0 1 timer 1 o verf l o w 2 s mod1 0 1 s m2
120 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.6 more about mode 1 ten bits a re tr a nsmitted (thro u gh txd), or received (thro u gh rxd): a st a rt bit (0), 8 d a t a bits (l s b first), a nd a stop bit (1). on receive, the stop bit goes into rb 8 in s con. in the at 8 9lp51rb2/rc2/ic2, the b au d r a te is determined either by the timer 1 overflow r a te, the timer 2 overflow r a te, or both. in this c a se one timer is for tr a nsmit a nd the other is for receive. fig u re 17-5 shows a simplified f u nction a l di a gr a m of the seri a l port in mode 1 a nd a ssoci a ted timings for tr a nsmit a nd receive. tr a nsmission is initi a ted by a ny instr u ction th a t u ses s buf a s a destin a tion register. the ?write to s buf? sign a l a lso lo a ds a ?1? into the 9th bit position of the tr a nsmit shift register a nd fl a gs the tx control u nit th a t a tr a nsmission is req u ested. tr a nsmission a ct ua lly commences a t s 1p1 of the m a chine cycle following the next ro llover in the divide-by-16 co u nter. th u s, the bit times a re synchronized to the divide-by-16 co u nter, not to the ?write to s buf? sign a l. the tr a nsmission begins when s end is a ctiv a ted, which p u ts the st a rt bit a t txd. one bit time l a ter, data is a ctiv a ted, which en a bles the o u tp u t bit of the tr a nsmit shift register to txd. the first shift p u lse occ u rs one bit time a fter th a t. as d a t a bits shift o u t to the right, ?0?s a re clocked in from the left. when the m s b of the d a t a byte is a t the o u tp u t position of the shift register, the ?1? th a t w a s initi a lly lo a ded into the 9th position is j u st to the left of the m s b, a nd a ll positions to the left of th a t cont a in ?0?s. this condition fl a gs the tx control u nit to do one l a st shift, then de a ctiv a te s end a nd set ti. this occ u rs a t the tenth divide-by-16 rollover a fter ?write to s buf.? reception is initi a ted by a 1-to-0 tr a nsition detected a t rxd. for this p u rpose, rxd is s a mpled a t a r a te of 16 times the est a blished b au d r a te. when a tr a nsition is detected, the divide-by-16 co u nter is immedi a tely reset, a nd 1ffh is written into the inp u t shift register. resetting the divide-by-16 co u nter a ligns its roll-overs with the bo u nd a ries of the incoming bit times. the 16 st a tes of the co u nter divide e a ch bit time into 16ths. at the 7th, 8 th, a nd 9th co u nter st a tes of e a ch bit time, the bit detector s a mples the v a l u e of rxd. the v a l u e a ccepted is the v a l u e th a t w a s seen in a t le a st 2 of the 3 s a mples. this is done to reject noise. in order to reject f a lse bits, if the v a l u e a ccepted d u ring the first bit time is not 0, the receive circ u its a re reset a nd the u nit contin u es looking for a nother 1-to-0 tr a nsition. if the st a rt bit is v a lid, it is shifted into the inp u t shift register, a nd reception of the rest of the fr a me proceeds. as d a t a bits come in from the right, ?1?s shift o u t to the left. when the st a rt bit a rrives a t the left- most position in the shift register, (which is a 9-bit register in mode 1), it fl a gs the rx control block to do one l a st shift, lo a d s buf a nd rb 8 , a nd set ri. the sign a l to lo a d s buf a nd rb 8 a nd to set ri is gener a ted if, a nd only if, the following conditions a re met a t the time the fin a l shift p u lse is gener a ted. ri = 0 a nd either s m2 = 0, or the received stop bit = 1 if either of these two conditions is not met, the received fr a me is irretriev a bly lost. if both condi- tions a re met, the stop bit goes into rb 8 , the 8 d a t a bits go into s buf, a nd ri is a ctiv a ted. at this time, whether or not the a bove conditions a re met, the u nit contin u es looking for a 1-to-0 tr a nsition in rxd.
121 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-5. s eri a l port mode 1 tx clock write to s buf internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 ?0? ?1? timer 1 overflow rxd rx clock rx clock rx control s tart s tart data s end s ample 16 16 tx control ti t i zero detector s buf txd internal bu s ?1? d q cl s load s buf s hift s hift 1ffh ri s end data s hift txd ti d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 s top bit tran s mit s tart bit 16 re s et s tart bit s top bit rx clock bit detector s ample time s s hift receive rxd ri timer 2 overflow tclk rclk ?0? ?0? ?1? ?1?
122 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 17.7 more about modes 2 and 3 eleven bits a re tr a nsmitted (thro u gh txd), or received (thro u gh rxd): a st a rt bit (0), 8 d a t a bits (l s b first), a progr a mm a ble 9th d a t a bit, a nd a stop bit (1). on tr a nsmit, the 9th d a t a bit (tb 8 ) c a n be a ssigned the v a l u e of ?0? or ?1?. on receive, the 9th d a t a bit goes into rb 8 in s con. the b au d r a te is progr a mm a ble to either 1/16 or 1/32 of the oscill a tor freq u ency in mode 2. mode 3 m a y h a ve a v a ri a ble b au d r a te gener a ted from either timer 1 or timer 2, depending on the st a te of rclk a nd tclk. fig u res 17-6 a nd 17-7 show a f u nction a l di a gr a m of the seri a l port in modes 2 a nd 3. the receive portion is ex a ctly the s a me a s in mode 1. the tr a nsmit portion differs from mode 1 only in the 9th bit of the tr a nsmit shift register. tr a nsmission is initi a ted by a ny instr u ction th a t u ses s buf a s a destin a tion register. the ?write to s buf? sign a l a lso lo a ds tb 8 into the 9th bit position of the tr a nsmit shift register a nd fl a gs the tx control u nit th a t a tr a nsmission is req u ested. tr a nsmission commences a t s 1p1 of the m a chine cycle following the next ro llover in the divide-by-16 co u nter. th u s, the bit times a re syn- chronized to the divide-by-16 co u nter, not to the ?write to s buf? sign a l. the tr a nsmission begins when s end is a ctiv a ted, which p u ts the st a rt bit a t txd. one bit time l a ter, data is a ctiv a ted, which en a bles the o u tp u t bit of the tr a nsmit shift register to txd. the first shift p u lse occ u rs one bit time a fter th a t. the first shift clocks a ?1? (the stop bit) into the 9th bit position of the shift register. there a fter, only ?0?s a re clocked in. th u s, a s d a t a bits shift o u t to the right, ?0?s a re clocked in from the left. when tb 8 is a t the o u tp u t position of the shift register, then the stop bit is j u st to the left of tb 8 , a nd a ll positions to the left of th a t cont a in ?0?s. this con- dition fl a gs the tx control u nit to do one l a st shift, then de a ctiv a te s end a nd set ti. this occ u rs a t the 11th divide-by-16 rollover a fter ?write to s buf.? reception is initi a ted by a 1-to-0 tr a nsition detected a t rxd. for this p u rpose, rxd is s a mpled a t a r a te of 16 times the est a blished b au d r a te. when a tr a nsition is detected, the divide-by-16 co u nter is immedi a tely reset, a nd 1ffh is written to the inp u t shift register. at the 7th, 8 th a nd 9th co u nter st a tes of e a ch bit time, the bit detector s a mples the v a l u e of rxd. the v a l u e a ccepted is the v a l u e th a t w a s seen in a t le a st 2 of the 3 s a mples. if the v a l u e a ccepted d u ring the first bit time is not 0, the receive circ u its a re reset a nd the u nit contin u es looking for a nother 1-to-0 tr a nsition. if the st a rt bit proves v a lid, it is shifted into the inp u t shift register, a nd reception of the rest of the fr a me proceeds. as d a t a bits come in from the right, ?1?s shift o u t to the left. when the st a rt bit a rrives a t the left- most position in the shift re gister (which in modes 2 a nd 3 is a 9-bit register), it fl a gs the rx con- trol block to do one l a st shift, lo a d s buf a nd rb 8 , a nd set ri. the sign a l to lo a d s buf a nd rb 8 a nd to set ri is gener a ted if, a nd only if, the following conditions a re met a t the time the fin a l shift p u lse is gener a ted: ri = 0, a nd either s m2 = 0 or the received 9th d a t a bit = 1 if either of these conditions is not met, the received fr a me is irretriev a bly lost, a nd ri is not set. if both conditions a re met, the received 9th d a t a bit goes into rb 8 , a nd the first 8 d a t a bits go into s buf. one bit time l a ter, whether the a bove conditions were met or not, the u nit contin u es look- ing for a 1-to-0 tr a nsition a t the rxd inp u t. note th a t the v a l u e of the received stop bit is irrelev a nt to s buf, rb 8 , or ri.
123 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-6. s eri a l port mode 2 s mod1 1 s mod1 0 internal bu s internal bu s cpu clock
124 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 17-7. s eri a l port mode 3 tx clock write to s buf s end data s hift txd s top bit gen ti d0 d1 d2 d3 d4 d5 d6 d7 tb 8 s top bit tran s mit s tart bit internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 timer 1 overflow rxd rx clock rx clock rx control s ta rt s ta rt data s ample 16 16 tx control ti zero detector s buf txd internal bu s tb 8 d q cl s load s buf s hift 1ffh s hift ri s end d0 d1 d2 d3 d4 d5 d6 d7 rb 8 s tart bit s top bit 16 re s et rx clock bit detector s ample time s s hift receive rxd ri s top bit timer 2 overflow tclk rclk ?0? ?0? ?1? ?1? ?0? ?1?
125 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18. enhanced serial peripheral interface the s eri a l peripher a l interf a ce ( s pi) a llows high-speed, f u ll-d u plex synchrono u s d a t a tr a nsfer between the at 8 9lp51rb2/rc2/ic2 a nd peripher a l devices or between m u ltiple microcon- troller devices, incl u ding m u ltiple m a sters a nd sl a ves on a single b u s. the s pi incl u des the following fe a t u res: ?f u ll-d u plex, 3-wire or 4-wire s ynchrono u s d a t a tr a nsfer ?m a ster or s l a ve oper a tion ?m a xim u m bit freq u ency = f s y s /2 ?l s b first or m s b first d a t a tr a nsfer ? s even progr a mm a ble bit r a tes or timer 1-b a sed b au d gener a tion (m a ster mode) ?end of tr a nsmission interr u pt fl a g ? write collision fl a g protection ?do u ble-b u ffered receive a nd tr a nsmit ?tr a nsmit b u ffer empty interr u pt fl a g ? mode f au lt (m a ster collision) detection a nd interr u pt ?w a ke u p from idle mode a block di a gr a m of the s pi is shown below in fig u re 1 8 -1 . figure 18-1. s pi block di a gr a m f periph 8- b it shift regi s ter read data buf f e r pin control logic spi control spi statu s regi s ter spi inter r up t re q ue s t inte r na l data bu s clock select spi clock (ma s ter) 7- b it divider spi control regi s ter 8 8 8 spif wcol spr1 mstr spr2 clo c k logic msb s m spen ssdis mstr cpol cpha spr1 spr0 mstr spen dord lsb s m m s miso mosi sck ss spr0 spen w r ite data buf f e r sserr modf tbie t1 ovf remap dord spr2 txe
126 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18.1 interface description the interconnection between m a ster a nd sl a ve devices with s pi is shown in fig u re . the fo u r pins in the interf a ce a re m a ster-in/ s l a ve-o u t (mi s o), m a ster-o u t/ s l a ve-in (mo s i), s eri a l clock ( s ck), a nd s l a ve s elect ( ss ). the m s tr bit in s pcon determines the directions of mi s o a nd mo s i. also notice th a t mo s i connects to mo s i a nd mi s o to mi s o. by def au lt ss is a n inp u t to both m a ster a nd sl a ve devices. the m a ster m u st drive the ss inp u t of e a ch sl a ve device independently. figure 18-2. s pi m a ster- s l a ve interconnection the loc a tion of the s pi pins is determined by the remap bit in s p s ta a s shown in t a ble 1 8 -1 . when remap = 0, the pins a re loc a ted in the s a me loc a tions on port 1 a s the at 8 9c51rb2/rc2/ic2. when remap = 1 the pins a re sh u ffled on port 1 to be comp a tible with at 8 9 s8 253 a nd at 8 9lp6440. note th a t the s pi-b a sed in- s ystem progr a mming (i s p) interf a ce a lw a ys u ses the remap = 1 pins reg a rdless of the remap setting. 18.1.1 spi serial clock (sck) this sign a l is u sed to synchronize the d a t a movement both in a nd o u t of the devices thro u gh their mo s i a nd mi s o lines. the s ck line is sh a red a mong a ll devices on the b u s. it is driven by the m a ster for eight clock cycles to exch a nge one byte on the seri a l lines. the s ck pin is a clock o u tp u t in m a ster mode a nd a clock inp u t in sl a ve mode. if m u ltiple m a sters a re present in a sys- tem, only one sho u ld drive the s ck line a t a time. in m a ster mode, the b au d r a te of s ck is determined by the s pr bits in s pcon. the s pr bits select a v a l u e from a 7-bit presc a ler on the system clock or the timer 1 overflow. in sl a ve mode the clock r a te is set by the m a ster device; the sl a ve need not table 18-1. s eri a l peripher a l interf a ce connections name function pin connection direction remap = 0 remap = 1 mstr = 1 mstr = 0 s ck s eri a l clock p1.6 p1.7 out in mi s om a ster in / s l a ve o u t p1.5 p1.6 in out mo s im a ster o u t / s l a ve in p1.7 p1.5 out in ss s l a ve s elect (active-low) p1.1 p1.4 in in 8-bit shift regi s ter ma s ter slave msb lsb msb lsb 8-bit shift regi s ter miso miso ssdis mosi mosi ss ss gpio ssdis v cc sck sck modf clock generator
127 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18.1.2 master output / slave input (mosi) this 1-bit sign a l is directly connected between the m a ster device a nd a ll sl a ve devices. the mo s i line is u sed to tr a nsfer d a t a in series from the m a ster to the sl a ve. therefore, it is a n o u t- p u t sign a l from the m a ster, a nd a n inp u t sign a l to a sl a ve. a byte ( 8 -bit word) is norm a lly tr a nsmitted most signific a nt bit (m s b) first, le a st signific a nt bit (l s b) l a st. the dord bit in s p s ta c a n ch a nge the d a t a ordering to l s b first a nd m s b l a st. all devices on the s a me b u s sho u ld sh a re the s a me d a t a order. if m u ltiple m a sters a re present in a system, only one sho u ld drive the mo s i line a t a time. 18.1.3 master input / slave output (miso) this 1-bit sign a l is directly connected between a ll sl a ve devices a nd a m a ster device. the mi s o line is u sed to tr a nsfer d a t a in series from a sl a ve to the m a ster. therefore, it is a n o u tp u t sign a l from the sl a ve, a nd a n inp u t sign a l to the m a ster. a byte ( 8 -bit word) is tr a nsmitted most signifi- c a nt bit (m s b) first, le a st signific a nt bit (l s b) l a st. the dord bit in s p s ta c a n ch a nge the d a t a ordering to l s b first a nf m s b l a st. all devices on the s a me b u s sho u ld sh a re the s a me d a t a order. when m u ltiple sl a ves a re present in a system, only the sl a ve with its ss inp u t low will drive mi s o. 18.1.4 slave select (ss ) e a ch sl a ve peripher a l is selected by one s l a ve s elect pin ( ss ). this sign a l m u st st a y low for a ny mess a ge for a sl a ve. it is obvio u s th a t only one m a ster c a n drive the network a t a time. the m a s- ter m a y select e a ch sl a ve device by softw a re thro u gh port pins. to prevent b u s conflicts on the mi s o line, only one sl a ve sho u ld be selected a t a time by the m a ster for a tr a nsmission. in a m a ster config u r a tion, the ss line c a n be u sed in conj u nction with the modf fl a g in the s pi s t a t u s register ( s p s ta) to prevent m u ltiple m a sters from driving mo s i a nd s ck (see error conditions). a high level on the ss pin p u ts the mi s o line of a s l a ve s pi in a high-imped a nce st a te. the ss pin c a n be u sed a s a gener a l-p u rpose i/o if the fo llowing conditions a re met: ? the device is config u red a s a m a ster a nd the ss di s control bit in s pcon is set. this kind of config u r a tion c a n be fo u nd when only one m a ster is driving the network a nd there is no w a y th a t the ss pin co u ld be p u lled low. therefore, the modf fl a g in the s p s ta will never be set (1) . ? the device is config u red a s a s l a ve with cpha a nd ss di s control bits set (2) . this kind of config u r a tion c a n h a ppen when the system comprises one m a ster a nd one s l a ve only. therefore, the device sho u ld a lw a ys be selected a nd there is no re a son th a t the m a ster u ses the ss pin to select the comm u nic a ting s l a ve device. note: 1. cle a ring ss di s control bit does not cle a r modf. 2. s peci a l c a re sho u ld be t a ken when setting ss di s control bit when cpha = ?0? bec au se in this mode the ss is u sed to st a rt the tr a nsmission on some devices. this req u irement does not a pply to the at 8 9lp51rb2/rc2/ic2 itself. the in- s ystem progr a mming (i s p) interf a ce a lso u ses the s pi pins. altho u gh the i s p protocol is s pi-b a sed, the ss pin h a s speci a l me a ning a nd m u st be driven by the m a ster a s a fr a me delim- iter. ss c a nnot be tied to gro u nd for i s p to f u nction correctly. when the s pi is config u red a s a m a ster (m s tr in s pcon is set), the oper a tion of the ss pin depends on the setting of the s l a ve s elect dis a ble bit, ss di s . if ss di s = 1, the ss pin is a gen- er a l p u rpose o u tp u t pin which does not a ffect the s pi system. typic a lly, the pin will be driving the ss pin of a n s pi s l a ve. if ss di s =0, ss m u st be held high to ens u re m a ster s pi oper a tion.
128 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary if the ss pin is driven low by peripher a l circ u itry when the s pi is config u red a s a m a ster with ss ig = 0, the s pi system interprets this a s a nother m a ster selecting the s pi a s a sl a ve a nd st a rting to send d a t a to it. to a void b u s contention, the s pi system t a kes the following a ctions: 1. the m s tr bit in s pcon is cle a red a nd the s pi system becomes a s l a ve. as a res u lt of the s pi becoming a s l a ve, the mo s i a nd s ck pins become inp u ts. 2. the modf fl a g in s p s ta i s s e t , a nd if the s pi interr u pt is en a bled, the interr u pt ro u - tine will be exec u ted. th u s, when interr u pt-driven s pi tr a nsmission is u sed in m a ster mode, a nd there exists a possi- bility th a t ss m a y be driven low, the interr u pt sho u ld a lw a ys check th a t the m s tr bit is still set. if the m s tr bit h a s been cle a red by a sl a ve select, it m u st be set by the u ser to re-en a ble s pi m a ster mode. 18.1.5 pin configuration when the s pi is en a bled ( s pen = 1), the d a t a direction of the mo s i, mi s o a nd s ck pins is au tom a tic a lly overridden a ccording to the m s tr bit a s shown in t a ble 1 8 -2 . the u ser need not reconfig u re the pins when switching from m a ster to sl a ve or vice-vers a . for more det a ils on port config u r a tion, refer to ?port config u r a tion? on p a ge 69 . . notes: 1. in these modes mo s i is a ctive only d u ring tr a nsfers. mo s i will be p u lled high between tr a ns- fers to a llow other m a sters to control the line. 2. in p u sh-p u ll mode mo s i is a ctive only d u ring tr a nsfers, otherwise it is trist a ted to prevent line contention. a we a k extern a l p u ll- u p m a y be req u ired to prevent mo s i from flo a ting. table 18-2. s pi pin config u r a tion a nd beh a vior when s pe = 1 pin mode master (mstr = 1) slave (mstr = 0) s ck q ua si-bidirection a lo u tp u tinp u t (intern a l p u ll- u p) p u sh-p u ll o u tp u to u tp u tinp u t (trist a te) inp u t-only no o u tp u t (trist a ted) inp u t (trist a te) open-dr a in o u tp u to u tp u t inp u t (extern a l p u ll- u p) mo s i q ua si-bidirection a lo u tp u t (1) inp u t (intern a l p u ll- u p) p u sh-p u ll o u tp u to u tp u t (2) inp u t (trist a te) inp u t-only no o u tp u t (trist a ted) inp u t (trist a te) open-dr a in o u tp u to u tp u t (1) inp u t (extern a l p u ll- u p) mi s o q ua si-bidirection a linp u t (intern a l p u ll- u p) o u tp u t ( ss = 0) intern a l p u ll- u p ( ss = 1) p u sh-p u ll o u tp u tinp u t (trist a te) o u tp u t ( ss = 0) tr i s t a ted ( ss = 1) inp u t-only inp u t (trist a te) no o u tp u t (trist a ted) open-dr a in o u tp u tinp u t (extern a l p u ll- u p) o u tp u t ( ss = 0) extern a l p u ll- u p ( ss = 1)
129 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18.2 master operation an s pi m a ster device initi a tes a ll d a t a tr a nsfers on the s pi b u s. the at 8 9lp51rb2/rc2/ic2 is config u red for m a ster oper a tion by setting m s tr = 1 in s pcon. writing to the s pi d a t a register ( s pdat) while in m a ster mode lo a ds the tr a nsmit b u ffer. if the s pi shift register is empty, the byte in the tr a nsmit b u ffer is moved to the shift register; the tr a nsmit b u ffer empty fl a g, txe, is set; a nd a tr a nsmission begins. the tr a nsfer m a y st a rt a fter a n initi a l del a y, while the clock gen- er a tor w a its for the next f u ll bit slot of the specified b au d r a te. the m a ster shifts the d a t a o u t seri a lly on the mo s i line while providing the seri a l shift clock on s ck. when the tr a nsfer fin- ishes, the s pif fl a g is set to ?1? a nd a n interr u pt req u est is gener a ted, if en a bled. the d a t a received from the a ddressed s pi sl a ve device is a lso tr a nsferred from the shift register to the receive b u ffer. therefore, the s pif bit fl a gs both the tr a nsmit-complete a nd receive-d a t a -re a dy conditions. the received d a t a is a ccessed by re a ding s pdat. while the txe fl a g is set, the tr a nsmit b u ffer is empty. txe c a n be cle a red by softw a re or by writing to s pdat. writing to s pdat will cle a r txe a nd lo a d the tr a nsmit b u ffer. the u ser m a y lo a d the b u ffer while the shift register is b u sy, i.e. before the c u rrent tr a nsfer completes. when the c u rrent tr a nsfer completes, the q u e u ed byte in the tr a nsmit b u ffer is moved to the shift regis- ter a nd the next tr a nsfer commences. txe will gener a te a n interr u pt if the s pi interr u pt is en a bled a nd if the enh bit in s p s ta is set. for m u lti-byte tr a nsfers, txe m a y be u sed to remove a ny de a d time between byte tr a nsmissions. the s pi m a ster c a n oper a te in two modes: m u lti-m a ster mode a nd single-m a ster mode. by def au lt, m u lti-m a ster mode is a ctive when ss ig = 0. in this mode, the ss inp u t is u sed to dis- a ble a m a ster device when a nother m a ster is a ccessing the b u s. when ss is driven low, the m a ster device becomes a sl a ve by cle a ring its m s tr bit a nd a mode f au lt is gener a ted by set- ting the modf bit in s p s ta. modf will gener a te a n interr u pt if en a bled. the m s tr bit m u st be set in softw a re before the device m a y become a m a ster a g a in. s ingle-m a ster mode is en a bled by setting ss ig = 1. in this mode ss is ignored a nd the m a ster is a lw a ys a ctive. ss m a y be u sed a s a gener a l p u rpose i/o in this mode. 18.3 slave operation when the at 8 9lp51rb2/rc2/ic2 is not config u red for m a ster oper a tion, m s tr = 0, it will oper- a te a s a n s pi sl a ve. in sl a ve mode, bytes a re shifted in thro u gh mo s i a nd o u t thro u gh mi s o by a m a ster device controlling the seri a l clock on s ck. when a byte h a s been tr a nsferred, the s pif fl a g is set to ?1? a nd a n interr u pt req u est is gener a ted, if en a bled. the d a t a received from the a ddressed m a ster device is a lso tr a nsferred from the shift register to the receive b u ffer. the received d a t a is a ccessed by re a ding s pdat. a sl a ve device c a nnot initi a te tr a nsfers. d a t a to be tr a nsferred to the m a ster device m u st be prelo a ded by writing to s pdat. writes to s pdat a re do u ble-b u ffered. the tr a nsmit b u ffer is lo a ded first a nd if the shift register is empty, the con- tents of the b u ffer will be tr a nsferred to the shift register. while the txe fl a g is set, the tr a nsmit b u ffer is empty. txe c a n be cle a red by softw a re or by writing to s pdat. writing to s pdat will cle a r txe a nd lo a d the tr a nsmit b u ffer. the u ser m a y lo a d the b u ffer while the shift register is b u sy, i.e. before the c u rrent tr a nsfer completes. when the c u rrent tr a nsfer completes, the q u e u ed byte in the tr a nsmit b u ffer is moved to the shift regis- ter a nd w a its for the m a ster to initi a te a nother tr a nsfer. txe will gener a te a n interr u pt if the s pi interr u pt is en a bled a nd if the enh bit in s p s ta is set. the s pi sl a ve c a n oper a te in two modes: 4-wire mode a nd 3-wire mode. by def au lt, 4-wire mode is a ctive when ss ig = 0. in this mode, the ss inp u t is u sed to en a ble/dis a ble the sl a ve device when a ddressed by a m a ster. when ss is driven low, the sl a ve device is en a bled a nd will
130 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary shift o u t d a t a on mi s o in response to the seri a l clock on s ck. while ss is high, the s pi sl a ve will rem a in sleeping with mi s o in a ctive. three-wire mode is en a bled by setting ss ig = 1. in this mode ss is ignored a nd the sl a ve is a lw a ys a ctive. ss m a y be u sed a s a gener a l p u rpose i/o in this mode. the dis a ble s l a ve o u tp u t bit, di ss o in s p s ta, m a y be u sed to dis a ble the mi s o line of a sl a ve device. di ss o c a n a llow sever a l sl a ve devices to sh a re mi s o while oper a ting in 3-wire mode. in this c a se some protocol other th a n ss m a y be u sed to determine which sl a ve is en a bled. 18.4 error conditions the following fl a gs in the s p s ta sign a l s pi error conditions: 18.4.1 mode fault (modf) mode f au lt error in m a ster mode s pi indic a tes th a t the level on the s l a ve s elect ( ss ) pin is inconsistent with the a ct ua l mode of the device. modf is set to w a rn th a t there m a y be a m u lti- m a ster conflict for system control. in this c a se, the s pi system is a ffected in the following w a ys: ?an s pi receiver/err or cpu interr u pt req u est is gener a ted ?the s pen bit in s pcon is cle a red. this dis a bles the s pi ?the m s tr bit in s pcon is cle a red when ss dis a ble ( ss di s ) bit in the s pcon register is cle a red, the modf fl a g is set when the ss sign a l becomes ?0?. however, a s st a ted before, for a system with one m a ster, if the ss pin of the m a ster device is p u lled low, there is no w a y th a t a nother m a ster a ttempts to drive the network. in this c a se, to prevent the modf fl a g from being set, softw a re c a n set the ss di s bit in the s pcon register a nd therefore m a king the ss pin a s a gener a l-p u rpose i/o pin. cle a ring the modf bit is a ccomplished by a re a d of s p s ta register with modf bit set, followed by a write to the s pcon register. s pen control bit m a y be restored to its origin a l set st a te a fter the modf bit h a s been cle a red. 18.4.2 write collision (wcol) a write collision (wcol) fl a g in the s p s ta is set when a write to the s pdat register is done d u ring a tr a nsmit seq u ence. wcol does not c au se a n interr u ption, a nd the tr a nsfer contin u es u ninterr u pted. cle a ring the wcol bit is done thro u gh a softw a re seq u ence of a n a ccess to s p s ta a nd a n a ccess to s pdat. 18.4.3 overrun condition an overr u n condition occ u rs when the m a ster device tries to send sever a l d a t a bytes a nd the s l a ve devise h a s not cle a red the s pif bit iss u ing from the previo u s d a t a byte tr a nsmitted. in this c a se, the receiver b u ffer cont a ins the byte sent a fter the s pif bit w a s l a st cle a red. a re a d of the s pdat ret u rns this byte. all others bytes a re lost. this condition is not detected by the s pi peripher a l.
131 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18.4.4 ss error flag (sserr) a s ynchrono u s s eri a l s l a ve error occ u rs when ss goes high before the end of a received d a t a in sl a ve mode. ss err does not c au se in interr u ption, this bit is cle a red by writing 0 to s pen bit (reset of the s pi st a te m a chine). 18.5 serial clock timing the cpha, cpol a nd s pr bits in s pcon control the sh a pe a nd r a te of s ck. the two s pr bits provide fo u r possible clock r a tes when the s pi is in m a ster mode. in sl a ve mode, the s pi will oper a te a t the r a te of the incoming s ck a s long a s it does not exceed the m a xim u mbit r a te. there a re a lso fo u r possible combin a tions of s ck ph a se a nd pol a rity with respect to the seri a l d a t a . cpha a nd cpol determine which form a t is u sed for tr a nsmission. the s pi d a t a tr a nsfer form a ts a re shown in fig u res 1 8 -3 a nd 1 8 -4 . to prevent glitches on s ck from disr u pting the interf a ce, cpha, cpol, a nd s pr sho u ld not be modified while the interf a ce is en a bled, a nd the m a ster device sho u ld be en a bled before the sl a ve device(s). figure 18-3. s pi tr a nsfer form a t with cpha = 0 note: *not defined b u t norm a lly m s b of ch a r a cter j u st received. figure 18-4. s pi tr a nsfer form a t with cpha = 1 note: *not defined b u t norm a lly l s b of previo u sly tr a nsmitted ch a r a cter. msb 6 5 4 3 2 1 lsb 1 2 3 4 5 6 7 8 msb * 65432 1 lsb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave)
132 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 18.6 registers notes: 1. s et u p the clock mode before en a bling the s pi: set a ll bits needed in s pcon except the s pen bit, then set s pen. 2. en a ble the m a ster s pi prior to the sl a ve device. 3. s l a ve echoes m a ster on the next tx if not lo a ded with new d a t a . table 18-3. s pcon ? s pi control register s pcon address = c3h reset v a l u e = 0001 0100b not bit address a ble s pr2 s pen ss di s m s tr cpol cpha s pr1 s pr0 bit76543210 symbol function s pr2 serial peripheral clock rate 2 s ee the description for s pr 1-0 s pen serial peripheral enable s pi = 1 en a bles the s pi ch a nnel a nd connects ss , mo s i, mi s o a nd s ck to pins p1.4, p1.5, p1.6, a nd p1.7. s pi = 0 dis a bles the s pi ch a nnel. ss di s slave select disable if ss di s = 0, the s pi will only oper a te in sl a ve mode if ss (p1.4) is p u lled low. when ss di s = 1, the s pi ignores ss in sl a ve mode a nd is a ctive whenever s pe ( s pcon.6) is set. when m s tr = 1 a nd ss di s = 0, ss is monitored for m a ster mode collisions. s etting ss di s = 1 will ignore collisions on ss . p1.4 m a y be u sed a s a reg u l a r i/o pin when ss ig = 1. m s tr master/slave select m s tr = 1 selects m a ster s pi mode. m s tr = 0 selects sl a ve s pi mode. cpol clock polarity when cpol = 1, s ck is high when idle. when cpol = 0, s ck of the m a ster device is low when not tr a nsmitting. ple a se refer to fig u re on s pi clock ph a se a nd pol a rity control. cpha clock phase the cpha bit together with the cpol bit controls the clock a nd d a t a rel a tionship between m a ster a nd sl a ve. ple a se refer to fig u re on s pi clock ph a se a nd pol a rity control. s pr1 s pr0 serial peripheral clock rate these two bits control the s ck r a te of the device config u red a s m a ster. s pr1 a nd s pr0 h a ve no effect on the sl a ve. the rel a tionship between s ck a nd the oscill a tor freq u ency, f o s c. , is a s follows: s pr2 s pr1 s pr0 s ck (t s ck = 0) 000f periph /2 001f periph /4 010f periph / 8 011f periph /16 100f periph /32 101f periph /64 110f periph /12 8 1 1 1 timer 1 overflow/2
133 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 18-4. s pdat ? s pi d a t a register s pdat address = c5h reset v a l u e = 0000 0000 not bit address a ble s pd7 s pd6 s pd5 s pd4 s pd3 s pd2 s pd1 s pd0 bit76543210 table 18-5. s p s ta ? s pi s t a t u s register s p s ta address = c4h reset v a l u e = 0000 0000b not bit address a ble s pif wcol ss err modf txe dord remap tbie bit76543210 symbol function s pif spi transfer complete interrupt flag when a seri a l tr a nsfer is complete, the s pif bit is set by h a rdw a re a nd a n interr u pt is gener a ted if e s p = 1. the s pif bit m a y be cle a red by softw a re or by re a ding the s pi st a t u s register followed by re a ding/writing the s pi d a t a register. wcol write collision flag the wcol bit is set by h a rdw a re if s pdat is written while the tr a nsmit b u ffer is f u ll. the ongoing tr a nsfer is not a ffected. wcol m a y be cle a red by softw a re or by re a ding the s pi st a t u s register followed by re a ding/writing the s pi d a t a register. ss err ss slave error flag s et by h a rdw a re when ss is de a sserted before the end of a received d a t a byte. modf mode fault flag modf is set by h a rdw a re when a m a ster mode collision is detected (m s tr = 1, ss ig = 0 a nd ss = 0) a nd a n interr u pt is gener a ted if e s p = 1. modf m u st be cle a red by softw a re. txe transmit buffer empty flag s et by h a rdw a re when the tr a nsmit b u ffer is lo a ded into the shift register, a llowing a new byte to be lo a ded. txe m u st be cle a red by softw a re. when enh = 1 a nd e s p = 1, txe will gener a te a n interr u pt. dord data order dord = 1 selects l s b first d a t a tr a nsmission. dord = 0 selects m s b first d a t a tr a nsmission. remap remap spi pins when cle a red the s pi pins a re in the def au lt loc a tions on port 1 th a t a re comp a tible with at 8 9c51rb2/rc2/ic2. when set the pins a re sh u ffled on port 1 to m a tch the at 8 9 s8 253 or at 8 9lp6440 devices. s ee t a ble 1 8 -1 . tbie tx buffer interrupt enable when tbie = 1, txe will gener a te a n s pi interr u pt if e s p = 1. when tbie = 0, txe does not gener a te a n interr u pt.
134 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19. two-wire serial interface the two-wire interf a ce (twi) is a bi-direction a l 2-wire seri a l comm u nic a tion st a nd a rd. it is designed prim a rily for simple b u t efficient integr a ted circ u it (ic) control. the system is comprised of two lines, s cl ( s eri a l clock) a nd s da ( s eri a l d a t a ) th a t c a rry inform a tion between the ics connected to them. the only extern a l h a rdw a re needed to implement the b u s is a single p u ll- u p resistor for e a ch of the twi b u s lines. all devices connected to the b u s h a ve individ ua l a ddresses, a nd mech a nisms for resolving b u s contention a re inherent in the twi protocol. the seri a l d a t a tr a nsfer is limited to 400kbit/s in st a nd a rd mode. v a rio u s comm u nic a tion config u r a - tions c a n be designed u sing this b u s. fig u re 19-1 shows a typic a l 2-wire b u s config u r a tion. any of the devices connected to the b u s c a n be m a ster or sl a ve. the two-wire interf a ce on the at 8 9lp51rb2/rc2/ic2 provides the following fe a t u res: ? s imple yet powerf u l a nd flexible comm u nic a tion interf a ce, only two b u s lines needed ? both m a ster a nd s l a ve oper a tion su pported ?device c a n oper a te a s tr a nsmitter or receiver ? 7-bit address s p a ce allows u p to 12 8 different s l a ve addresses ?m u lti-m a ster arbitr a tion su pport ? up to 400 khz d a t a tr a nsfer s peed ?f u lly progr a mm a ble s l a ve address with gener a l c a ll su pport note: the twi is a v a il a ble on both the at 8 9lp51rb2 a nd at 8 9lp51rc2 where a s it w a s not a v a il a ble on the at 8 9c51rb2 a nd at 8 9c51rc2. the twi is not a v a il a ble in the pdip p a ck a ge. figure 19-1. two-wire b u s config u r a tion as depicted in fig u re 19-1 , both b u s lines a re connected to the positive s u pply volt a ge thro u gh p u ll- u p resistors. the b u s drivers of a ll twi-compli a nt devices a re open-dr a in or open-collector. this implements a wired-and f u nction which is essenti a l to the oper a tion of the interf a ce. a low level on a twi b u s line is gener a ted when one or more twi devices o u tp u t a zero. a high level is o u tp u t when a ll twi devices trist a te their o u tp u ts, a llowing the p u ll- u p resistors to p u ll the line high. note th a t a ll at 8 9lp devices connected to the twi b u s m u st be powered in order to a llow a ny b u s oper a tion. the n u mber of devices th a t c a n be connected to the b u s is only limited by the b u s c a p a cit a nce limit of 400 pf a nd the 7-bit sl a ve a ddress sp a ce. device 1 device 2 device 3 device n s da s cl ........ r1 r2 v cc
135 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.1 data transfer and frame format 19.1.1 transferring bits e a ch d a t a bit tr a nsferred on the twi b u s is a ccomp a nied by a p u lse on the clock line. the level of the d a t a line m u st be st a ble when the clock line is high. the only exception to this r u le is for gener a ting st a rt a nd stop conditions. figure 19-2. d a t a v a lidity 19.1.2 start and stop conditions the m a ster initi a tes a nd termin a tes a d a t a tr a nsmission. the tr a nsmission is initi a ted when the m a ster iss u es a s tart condition on the b u s, a nd it is termin a ted when the m a ster iss u es a s top condition. between a s tart a nd a s top condition, the b u s is considered b u sy, a nd no other m a ster sho u ld try to seize control of the b u s. a speci a l c a se occ u rs when a new s tart condition is iss u ed between a s tart a nd s top condition. this is referred to a s a repeated s tart condition, a nd is u sed when the m a ster wishes to initi a te a new tr a nsfer witho u t relin- q u ishing control of the b u s. after a repeated s tart, the b u s is considered b u sy u ntil the next s top. this is identic a l to the s tart beh a vior, a nd therefore s tart is u sed to describe both s tart a nd repeated s tart for the rem a inder of this d a t a sheet, u nless otherwise noted. as depicted below, s tart a nd s top conditions a re sign a lled by ch a nging the level of the s da line when the s cl line is high. figure 19-3. s tart, repeated s tart, a nd s top conditions 19.1.3 address packet format all a ddress p a ckets tr a nsmitted on the twi b u s a re nine bits long, consisting of seven a ddress bits, one read/write control bit a nd a n a cknowledge bit. if the read/write bit is set, a re a d oper a tion is to be performed, otherwise a write oper a tion sho u ld be performed. when a sl a ve recognizes th a t it is being a ddressed, it sho u ld a cknowledge by p u lling s da low in the ninth s cl (ack) cycle. if the a ddressed s l a ve is b u sy, or for some other re a son c a n not service the m a s- sda scl data sta b le data sta b le data change sda scl start stop repeated start stop start
136 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ter?s req u est, the s da line sho u ld be left high in the ack clock cycle. the m a ster c a n then tr a nsmit a s top condition, or a repeated s tart condition to initi a te a new tr a nsmission. an a ddress p a cket consisting of a sl a ve a ddress a nd a read or a write bit is c a lled s la+r or s la+w, respectively. the m s b of the a ddress byte is tr a nsmitted first. s l a ve a ddresses c a n freely be a lloc a ted by the designer, b u t the a ddress 0000 000 is reserved for a gener a l c a ll. when a gener a l c a ll is iss u ed, a ll sl a ves sho u ld respond by p u lling the s da line low in the ack cycle. a gener a l c a ll is u sed when a m a ster wishes to tr a nsmit the s a me mess a ge to sever a l sl a ves in the system. when the gener a l c a ll a ddress followed by a write bit is tr a nsmitted on the b u s, a ll sl a ves set u p to a cknowledge the gener a l c a ll will p u ll the s da line low in the ack cycle. the following d a t a p a ckets will then be received by a ll the sl a ves th a t a cknowledged the gener a l c a ll. note th a t tr a nsmitting the gener a l c a ll a ddress followed by a re a d bit is me a ningless, a s this wo u ld c au se contention if sever a l sl a ves st a rted tr a nsmitting different d a t a . all a ddresses of the form a t 1111 xxx sho u ld be reserved for f u t u re p u rposes. figure 19-4. address p a cket form a t 19.1.4 data packet format all d a t a p a ckets tr a nsmitted on the twi b u s a re nine bits long, consisting of one d a t a byte a nd a n a cknowledge bit. d u ring a d a t a tr a nsfer, the m a ster gener a tes the clock a nd the s tart a nd s top conditions, while the receiver is responsible for a cknowledging the reception. an acknowledge (ack) is sign a lled by the receiver p u lling the s da line low d u ring the ninth s cl cycle. if the receiver le a ves the s da line high, a nack is sign a lled. when the receiver h a s received the l a st byte, or for some re a son c a nnot receive a ny more bytes, it sho u ld inform the tr a nsmitter by sending a nack a fter the fin a l byte. the m s b of the d a t a byte is tr a nsmitted first. figure 19-5. d a t a p a cket form a t sda scl start 12 789 addr msb addr lsb r/w ack 12 789 data msb data lsb ack aggregate sda sda from tr a n s mitter sda from receiver scl from ma s ter sla+r/w data byte stop, repeated start, or next data byte
137 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.1.5 combining address and data packets into a transmission a tr a nsmission b a sic a lly consists of a s tart condition, a s la+r/w, one or more d a t a p a ckets a nd a s top condition. an empty mess a ge, consisting of a s tart followed by a s top condi- tion, is illeg a l. note th a t the wired-anding of the s cl line c a n be u sed to implement h a ndsh a king between the m a ster a nd the s l a ve. the s l a ve c a n extend the s cl low period by p u lling the s cl line low. this is u sef u l if the clock speed set u p by the m a ster is too f a st for the s l a ve, or the s l a ve needs extr a time for processing between the d a t a tr a nsmissions. the s l a ve extending the s cl low period will not a ffect the s cl high period, which is determined by the m a ster. as a conseq u ence, the s l a ve c a n red u ce the twi d a t a tr a nsfer speed by prolonging the s cl d u ty cycle. fig u re 19-6 shows a typic a l d a t a tr a nsmission. note th a t sever a l d a t a bytes c a n be tr a nsmitted between the s la+r/w a nd the s top condition, depending on the softw a re protocol imple- mented by the a pplic a tion softw a re. figure 19-6. typic a l d a t a tr a nsmission 19.2 multi-master bus systems, arbitration and synchronization the twi protocol a llows b u s systems with sever a l m a sters. s peci a l concerns h a ve been t a ken in order to ens u re th a t tr a nsmissions will proceed a s norm a l, even if two or more m a sters initi a te a tr a nsmission a t the s a me time. two problems a rise in m u lti-m a ster systems: ?an a lgorithm m u st be implemented a llowing only one of the m a sters to complete the tr a nsmission. all other m a sters sho u ld ce a se tr a nsmission when they discover th a t they h a ve lost the selection process. this selection process is c a lled a rbitr a tion. when a contending m a ster discovers th a t it h a s lost the a rbitr a tion process, it sho u ld immedi a tely switch to s l a ve mode to check whether it is being a ddressed by the winning m a ster. the f a ct th a t m u ltiple m a sters h a ve st a rted tr a nsmission a t the s a me time sho u ld not be detect a ble to the sl a ves (i.e., the d a t a being tr a nsferred on the b u s m u st not be corr u pted). ? different m a sters m a y u se different s cl freq u encies. a scheme m u st be devised to synchronize the seri a l clocks from a ll m a sters, in order to let the tr a nsmission proceed in a lockstep f a shion. this will f a cilit a te the a rbitr a tion process. the wired-anding of the b u s lines is u sed to solve both these problems. the seri a l clocks from a ll m a sters will be wired-anded, yielding a combined clock with a high period eq ua l to the one from the m a ster with the shortest high period. the low period of the combined clock is eq ua l to the low period of the m a ster with the longest low period. note th a t a ll m a sters listen to the s cl line, effectively st a rting to co u nt their s cl high a nd low time-o u t periods when the combined s cl line goes high or low, respectively. 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop
138 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 19-7. s cl s ynchroniz a tion between m u ltiple m a sters arbitr a tion is c a rried o u t by a ll m a sters contin u o u sly monitoring the s da line a fter o u tp u tting d a t a . if the v a l u e re a d from the s da line does not m a tch the v a l u e the m a ster h a d o u tp u t, it h a s lost the a rbitr a tion. note th a t a m a ster c a n only lose a rbitr a tion when it o u tp u ts a high s da v a l u e while a nother m a ster o u tp u ts a low v a l u e. the losing m a ster sho u ld immedi a tely go to s l a ve mode, checking if it is being a ddressed by the winning m a ster. the s da line sho u ld be left high, b u t losing m a sters a re a llowed to gener a te a clock sign a l u ntil the end of the c u rrent d a t a or a ddress p a cket. arbitr a tion will contin u e u ntil only one m a ster rem a ins, a nd this m a y t a ke m a ny bits. if sever a l m a sters a re trying to a ddress the s a me sl a ve, a rbitr a tion will contin u e into the d a t a p a cket. figure 19-8. arbitr a tion between two m a sters note th a t a rbitr a tion is not a llowed between: ? a repeated s tart condition a nd a d a t a bit. ?a s top condition a nd a d a t a bit. ? a repeated s ta rt a nd a s top condition. ta low ta high scl from ma s ter a scl from ma s ter b scl b u s line tb low tb high ma s ter s start counting low period ma s ter s start counting high period sda from ma s ter a sda from m sda line synchronized scl line start ma s ter a lo s e s ar b itration, sda a sda
139 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary it is the u ser softw a re?s responsibility to ens u re th a t these illeg a l a rbitr a tion conditions never occ u r. this implies th a t in m u lti-m a ster systems, a ll d a t a tr a nsfers m u st u se the s a me composi- tion of s la+r/w a nd d a t a p a ckets. in other words: all tr a nsmissions m u st cont a in the s a me n u mber of d a t a p a ckets, otherwise the res u lt of the a rbitr a tion is u ndefined. 19.3 overview of the twi module the twi mod u le is comprised of sever a l s u bmod u les, a s shown in fig u re 19-9 . all registers dr a wn in a thick line a re a ccessible thro u gh the at 8 9lp d a t a b u s. figure 19-9. overview of the twi mod u le 19.3.1 scl and sda pins these pins interf a ce the twi with the rest of the mcu system. the o u tp u t drivers cont a in a slew- r a te limiter in order to conform to the twi specific a tion. the inp u t st a ges cont a in a spike s u p- pression u nit removing spikes shorter th a n 50 ns. 19.3.2 bit rate generator unit this u nit controls the period of s cl when oper a ting in a m a ster mode. the s cl period is con- trolled by settings in the ss con register. s l a ve oper a tion does not depend on the bit r a te setting, b u t the cpu clock freq u ency in the sl a ve m u st be a t le a st 16 times higher th a n the s cl freq u ency. note th a t sl a ves m a y prolong the s cl low period, thereby red u cing the a ver a ge twi b u s clock period. the s cl freq u ency is gener a ted a ccording to t a ble 19-1 . twi unit addre ss regi s ter (ssadr) addre ss match unit addre ss comparator control unit control regi s ter (sscon) statu s regi s ter (sscs) state machine and statu s control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator timer 1 overflow pre s caler bu s interface unit start / stop control ar b itration detection ack spike suppre ss ion addre ss /data shift regi s ter (ssdat)
140 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.3.3 bus interface unit this u nit cont a ins the d a t a a nd address s hift register ( ss dat), a s tart/ s top controller a nd arbitr a tion detection h a rdw a re. the ss dat cont a ins the a ddress or d a t a bytes to be tr a nsmit- ted, or the a ddress or d a t a bytes received. in a ddition to the 8 -bit ss dat, the b u s interf a ce unit a lso cont a ins a register cont a ining the (n)ack bit to be tr a nsmitted or received. this (n)ack register is not directly a ccessible by the a pplic a tion softw a re. however, when receiving, it c a n be set or cle a red by m a nip u l a ting the twi control register ( ss con). when in tr a nsmitter mode, the v a l u e of the received (n)ack bit c a n be determined by the v a l u e in the ss c s . the s tart/ s top controller is responsible for gener a tion a nd detection of s tart, repeated s tart, a nd s top conditions. if the twi h a s initi a ted a tr a nsmission a s m a ster, the arbitr a tion detection h a rdw a re contin u - o u sly monitors the tr a nsmission trying to determine if a rbitr a tion is in process. if the twi h a s lost a n a rbitr a tion, the control unit is informed. correct a ction c a n then be t a ken a nd a ppropri a te st a t u s codes gener a ted. 19.3.4 address match unit the address m a tch u nit checks if received a ddress bytes m a tch the 7-bit a ddress in the twi address register ( ss adr). if the twi gener a l c a ll recognition en a ble (gc) bit in the ss adr is written to one, a ll incoming a ddress bits will a lso be comp a red a g a inst the gener a l c a ll a ddress. upon a n a ddress m a tch, the control u nit is informed, a llowing correct a ction to be t a ken. the twi m a y or m a y not a cknowledge its a ddress, depending on settings in the ss con. 19.3.5 control unit the control u nit monitors the twi b u s a nd gener a tes responses corresponding to settings in the twi control register ( ss con). when a n event req u iring the a ttention of the a pplic a tion occ u rs on the twi b u s, the twi interr u pt fl a g ( s i) is a sserted. in the next clock cycle, the twi s t a t u s register ( ss c s ) is u pd a ted with a st a t u s code identifying the event. the ss c s only cont a ins relev a nt st a t u s inform a tion when the twi interr u pt fl a g is a sserted. at a ll other times, the ss c s cont a ins a speci a l st a t u s code indic a ting th a t no relev a nt st a t u s inform a tion is a v a il a ble. as long a s the s i fl a g is set, the s cl line is held low. this a llows the a pplic a tion softw a re to complete its t a sks before a llowing the twi tr a nsmission to contin u e. the s i fl a g is set in the following sit ua tions: table 19-1. twi bit r a te config u r a tion cr2 cr1 cr0 f osca division bit rate (khz) f osca = 12 mhz f osca = 16 mhz 0 0 0 256 47 62.5 0 0 1 224 53.5 71.5 0 1 0 192 62.5 8 3 0 1 1 160 75 100 100un u sed 1 0 1 120 100 133.3 1 1 0 60 200 266.6 111 96 x timer 1 overflow 0.5 < b au d < 62.5 0.67 < b au d < 8 3
141 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ? after the twi h a s tr a nsmitted a s tart/repeated s tart condition. ? after the twi h a s tr a nsmitted s la+r/w. ? after the twi h a s tr a nsmitted a n a ddress byte. ? after the twi h a s lost a rbitr a tion. ? after the twi h a s been a ddressed by own sl a ve a ddress or gener a l c a ll. ? after the twi h a s received a d a t a byte. ?after a s top or repeated s ta rt h a s been received while still a ddressed a s a s l a ve. ? when a b u s error h a s occ u rred d u e to a n illeg a l s ta rt o r s top condition. 19.4 register overview table 19-2. ss con ? two-wire control register ss con address = aah reset v a l u e = x000 00xxb not bit address a ble cr2 ss ie s ta s to s i aa cr1 cr0 bit76543210 symbol function cr2 bit control rate 2 s ets the bit r a te for twi m a ster mode a long with c1 a nd cr0. s ee t a ble 19-1 . ss ie two-wire serial interface enable s et to en a ble the twi. cle a r to dis a ble the twi. s ta start flag s et to send a s tart condition on the b u s. m u st be cle a red by softw a re. s to stop flag s et to send a s top condition on the b u s. cle a red au tom a tic a lly by h a rdw a re when the s top occ u rs. s i two-wire interface interrupt flag s et by h a rdw a re when the twi req u ests a n interr u pt. s i m u st be cle a red by softw a re. while s i is set, the s cl low period is stretched. note th a t cle a ring this fl a g st a rts the oper a tion of the twi, so a ll a ccesses to the othe r twi registers ( ss adr, ss c s a nd ss dat) m u st be complete before cle a ring this fl a g. aa assert acknowledge flag cle a r in m a ster a nd sl a ve receiver modes, to force a not a cknowledge (high level on s da). cle a r to dis a ble s la or gca recognition. s et to recognize s la or gca (if gc set) for entering sl a ve receiver or tr a nsmitter modes. s et in m a ster a nd sl a ve receiver modes, to force a n a cknowledge (low level on s da). this bit h a s no effect when in m a ster tr a nsmitter mode. by cle a ring aa to zero, the device c a n be virt ua lly disconnected from the two-wire s eri a l b u s tempor a rily. address recognition c a n then be res u med by setting the aa bit to one a g a in. cr1 bit control rate 1 s ets the bit r a te for twi m a ster mode a long with c0 a nd cr2. s ee t a ble 19-1 . cr0 bit control rate 02 s ets the bit r a te for twi m a ster mode a long with c1 a nd cr2. s ee t a ble 19-1 .
142 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.5 using the twi the at 8 9lp twi is byte-oriented a nd interr u pt b a sed. interr u pts a re iss u ed a fter a ll b u s events, like reception of a byte or tr a nsmission of a s tart condition. bec au se the twi is interr u pt- b a sed, the a pplic a tion softw a re is free to c a rry on other oper a tions d u ring a twi byte tr a nsfer. note th a t the twi interr u pt en a ble (etwi) bit in ie2 together with the glob a l interr u pt en a ble bit in ea a llow the a pplic a tion to decide whether or not a ssertion of the s i fl a g sho u ld gener a te a n table 19-3. ss c s ? two-wire s t a t u s register ss c s address = abh reset v a l u e = 1111 1000b not bit address a ble s c7 s c6 s c5 s c4 s c3000 bit76543210 symbol function s c 7-0 two-wire interface status the c u rrent st a t u s code of the twi logic a nd seri a l b u s. s ee t a ble 19-6 thro u gh t a ble 19-10 for a description of the st a t u s codes. note th a t the three le a st signific a nt bits a lw a ys re a d a s zero. the s t a t u s code is v a lid only while s i rem a ins set. table 19-4. ss adr ? two-wire address register ss adr address = ach reset v a l u e = 1111 1110b not bit address a ble s a6 s a5 s a4 s a3 s a2 s a1 s a0 gc bit76543210 symbol function s a 6-0 two-wire interface slave address the twi will only respond to sl a ve a ddresses th a t m a tch this 7-bit a ddress. gc general call enable s et to en a ble gener a l c a ll a ddress (00h) recognition. cle a r to dis a ble gener a l c a ll a ddress recognition. table 19-5. ss dat ? two-wire d a t a register ss dat address = adh reset v a l u e = 1111 1111b not bit address a ble s d7 s d6 s d5 s d4 s d3 s d2 s d1 s d0 bit76543210 symbol function s d 7-0 two-wire interface serial data writes to ss dat q u e u e the next a ddress or d a t a byte for tr a nsmission. re a ds from ss dat ret u rn the l a st a ddress or d a t a byte present on the b u s. writes/re a ds to/from ss dat m u st occ u r only while s i is set. writes to ss dat while s i=0 a re ignored. re a ds from ss dat while s i=0 m a y ret u rn r a ndom d a t a .
143 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary interr u pt req u est. if the twe bit is cle a red, the a pplic a tion m u st poll the s i fl a g in order to detect a ctions on the twi b u s. when the s i fl a g is a sserted, the twi h a s finished a n oper a tion a nd a w a its a pplic a tion response. in this c a se, the twi s t a t u s register ( ss c s ) cont a ins a v a l u e indic a ting the c u rrent st a te of the twi b u s. the a pplic a tion softw a re c a n then decide how the twi sho u ld beh a ve in the next twi b u s cycle by m a nip u l a ting the ss con a nd ss dat registers. fig u re 19-10 is a simple ex a mple of how the a pplic a tion c a n interf a ce to the twi h a rdw a re. in this ex a mple, a m a ster wishes to tr a nsmit a single d a t a byte to a s l a ve. this description is q u ite a bstr a ct, a more det a iled expl a n a tion follows l a ter in this section. a simple code ex a mple imple- menting the desired beh a vior is a lso presented. figure 19-10. interf a cing the applic a tion to the twi in a typic a l tr a nsmission 1. the first step in a twi tr a nsmission is to tr a nsmit a s tart condition. this is done by writing a specific v a l u e into ss con, instr u cting the twi h a rdw a re to tr a nsmit a s ta rt condition. which v a l u e to write is described l a ter on. however, it is import a nt th a t the s i bit is cle a red in the v a l u e written. the twi will not st a rt a ny oper a tion a s long a s the s i bit in ss con is set. immedi a tely a fter the a pplic a tion h a s cle a red s i, the twi will initi- a te tr a nsmission of the s tart condition. 2. when the s tart condition h a s been tr a nsmitted, the s i fl a g in ss con is set, a nd ss c s is u pd a ted with a st a t u s code indic a ting th a t the s tart condition h a s s u ccess- f u lly been sent. 3. the a pplic a tion softw a re sho u ld now ex a mine the v a l u e of ss c s , to m a ke s u re th a t the s tart condition w a s s u ccessf u lly tr a nsmitted. if ss c s indic a tes otherwise, the a ppli- c a tion softw a re might t a ke some speci a l a ction, like c a lling a n error ro u tine. ass u ming th a t the st a t u s code is a s expected, the a pplic a tion m u st lo a d s la+w into ss dat. remember th a t ss dat is u sed both for a ddress a nd d a t a . after ss dat h a s been lo a ded with the desired s la+w, a specific v a l u e m u st be written to ss con, instr u cting the twi h a rdw a re to tr a nsmit the s la+w present in ss dat. which v a l u e to write is described l a ter on. however, it is import a nt th a t the s i bit is cle a red in the v a l u e written. the twi will not st a rt a ny oper a tion a s long a s the s i bit in ss con is set. immedi a tely a fter the a pplic a tion h a s cle a red s i, the twi will initi a te tr a nsmission of the a ddress p a cket. start sla+w a data a stop 1. application write s to sscon to initiate tran s mi ss ion of start 2. si s et. statu s code indicate s start condition s ent 4. si s et. statu s code indicate s sla+w s ent, ack received 6. si s et. statu s code indicate s data s ent, ack received 3 . check sscs to s ee if start wa s s ent. application load s sla+w into ssdat, and load s appropriate control s ignal s into sscon, making s ure that si i s written to zero and sta i s written to zero. 5. check sscs to s ee if sla+w wa s s ent and ack received. application load s data into ssdat, and load s appropriate control s ignal s into sscon, making s ure that si i s written to zero. 7. check sscs to s ee if data wa s s ent and ack received. application load s appropriate control s ignal s to s end stop into sscon, making s ure that si i s written to zero. twi b u s indicate s si s et application action twi hardware action
144 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 4. when the a ddress p a cket h a s been tr a nsmitted, the s i fl a g in ss con is set, a nd ss c s is u pd a ted with a st a t u s code indic a ting th a t the a ddress p a cket h a s s u ccessf u lly been sent. the st a t u s code will a lso reflect whether a sl a ve a cknowledged the p a cket or not. 5. the a pplic a tion softw a re sho u ld now ex a mine the v a l u e of ss c s , to m a ke s u re th a t the a ddress p a cket w a s s u ccessf u lly tr a nsmitted, a nd th a t the v a l u e of the ack bit w a s a s expected. if ss c s indic a tes otherwise, the a pplic a tion softw a re might t a ke some spe- ci a l a ction, like c a lling a n error ro u tine. ass u ming th a t the st a t u s code is a s expected, the a pplic a tion m u st lo a d a d a t a p a cket into ss dat. su bseq u ently, a specific v a l u e m u st be written to ss con, instr u cting the twi h a rdw a re to tr a nsmit the d a t a p a cket present in ss dat. which v a l u e to write is described l a ter on. however, it is import a nt th a t the s i bit is cle a red in the v a l u e written. the twi will not st a rt a ny oper a tion a s long a s the s i bit in ss con is set. immedi a tely a fter the a pplic a tion h a s cle a red s i, the twi will initi a te tr a nsmission of the d a t a p a cket. 6. when the d a t a p a cket h a s been tr a nsmitted, the s i fl a g in ss con is set, a nd ss c s is u pd a ted with a st a t u s code indic a ting th a t the d a t a p a cket h a s s u ccessf u lly been sent. the st a t u s code will a lso reflect whether a sl a ve a cknowledged the p a cket or not. 7. the a pplic a tion softw a re sho u ld now ex a mine the v a l u e of ss c s , to m a ke s u re th a t the d a t a p a cket w a s s u ccessf u lly tr a nsmitted, a nd th a t the v a l u e of the ack bit w a s a s expected. if ss c s indic a tes otherwise, the a pplic a tion softw a re might t a ke some spe- ci a l a ction, like c a lling a n error ro u tine. ass u ming th a t the st a t u s code is a s expected, the a pplic a tion m u st write a specific v a l u e to ss con, instr u cting the twi h a rdw a re to tr a nsmit a s top condition. which v a l u e to write is described l a ter on. however, it is import a nt th a t the s i bit is cle a red in the v a l u e written. the twi will not st a rt a ny oper a - tion a s long a s the s i bit in ss con is set. immedi a tely a fter the a pplic a tion h a s cle a red s i, the twi will initi a te tr a nsmission of the s top condition. note th a t s i is not set a fter a s top condition h a s been sent. even tho u gh this ex a mple is simple, it shows the principles involved in a ll twi tr a nsmissions. these c a n be s u mm a rized a s follows: ? when the twi h a s finished a n oper a tion a nd expects a pplic a tion response, the s i fl a g is set. the s cl line is p u lled low u ntil s i is cle a red. ? when the s i fl a g is set, the u ser m u st u pd a te a ll twi registers with the v a l u e relev a nt for the next twi b u s cycle. as a n ex a mple, ss dat m u st be lo a ded with the v a l u e to be tr a nsmitted in the next b u s cycle. ?after a ll twi register u pd a tes a nd other pending a pplic a tion softw a re t a sks h a ve been completed, ss con is written. when writing ss con, the s i bit sho u ld be cle a red. the twi will then commence exec u ting wh a tever oper a tion w a s specified by the ss con setting. 19.6 transmission modes the twi c a n oper a te in one of fo u r m a jor modes. these a re n a med m a ster tr a nsmitter (mt), m a ster receiver (mr), s l a ve tr a nsmitter ( s t) a nd s l a ve receiver ( s r). s ever a l of these modes c a n be u sed in the s a me a pplic a tion. as a n ex a mple, the twi c a n u se mt mode to write d a t a into a twi eeprom, mr mode to re a d the d a t a b a ck from the eeprom. if other m a sters a re present in the system, some of these might tr a nsmit d a t a to the twi, a nd then s r mode wo u ld be u sed. it is the a pplic a tion softw a re th a t decides which modes a re leg a l. the following sections describe e a ch of these modes. possible st a t u s codes a re described a long with fig u res det a iling d a t a tr a nsmission in e a ch of the modes. these fig u res cont a in the following a bbrevi a tions:
145 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary s : s tart condition rs: repeated s tart condition r: re a d bit (high level a t s da) w: write bit (low level a t s da) a: acknowledge bit (low level a t s da) a : not a cknowledge bit (high level a t s da) d a t a : 8 -bit d a t a byte p: s top condition s la: s l a ve address in fig u re 19-11 to fig u re 19-14 , circles a re u sed to indic a te th a t the s i fl a g is set. the n u mbers in the circles show the st a t u s code held in ss c s . at these points, a ctions m u st be t a ken by the a pplic a tion to contin u e or complete the twi tr a nsfer. the twi tr a nsfer is s u spended u ntil the s i fl a g is cle a red by softw a re. when the s i fl a g is set, the st a t u s code in ss c s is u sed to determine the a ppropri a te softw a re a ction. for e a ch st a t u s code, the req u ired softw a re a ction a nd det a ils of the following seri a l tr a nsfer a re given in t a ble 19-6 to t a ble 19-9 . 19.6.1 master transmitter mode in the m a ster tr a nsmitter mode, a n u mber of d a t a bytes a re tr a nsmitted to a s l a ve receiver. in order to enter a m a ster mode, a s tart condition m u st be tr a nsmitted. the form a t of the follow- ing a ddress p a cket determines whether m a ster tr a nsmitter or m a ster receiver mode is to be entered. if s la+w is tr a nsmitted, mt mode is entered, if s la+r is tr a nsmitted, mr mode is entered. a s tart condition is sent by writing the following v a l u e to ss con: ss ie m u st be set to en a ble the two-wire s eri a l interf a ce, s ta m u st be written to one to tr a nsmit a s tart condition a nd s i m u st be cle a red. the twi will then test the two-wire s eri a l b u s a nd gener a te a s tart condition a s soon a s the b u s becomes free. after a s tart condition h a s been tr a nsmitted, the s i fl a g is set by h a rdw a re, a nd the st a t u s code in ss c s will be 0 8 h (see t a ble 19-6 ). in order to enter mt mode, s la+w m u st be tr a nsmitted. this is done by writing s la+w to ss dat. there a fter the s i bit sho u ld be cle a red to contin u e the tr a nsfer. when s la+w h a s been tr a nsmitted a nd a n a cknowledgment bit h a s been received, s i is set a g a in a nd a n u mber of st a t u s codes in ss c s a re possible. possible st a t u s codes in m a ster mode a re 1 8 h, 20h, or 3 8 h. the a ppropri a te a ction to be t a ken for e a ch of these st a t u s codes is det a iled in t a ble 19-6 . after s la+w h a s been s u ccessf u lly tr a nsmitted, a d a t a p a cket sho u ld be tr a nsmitted. this is done by writing the d a t a byte to ss dat. ss dat m u st only be written when s i is high. if not, the a ccess will be disc a rded a nd the previo u s v a l u e will be tr a nsmitted. after u pd a ting ss dat, the s i bit sho u ld be cle a red to contin u e the tr a nsfer. this scheme is repe a ted u ntil the l a st byte h a s been sent a nd the tr a nsfer is ended by gener a ting a s top condition or a repe a ted s tart con- dition. a s top condition is gener a ted by writing the following v a l u e to ss con: ss con cr2 ss ie s ta s to s i aa cr1 cr0 v a l u ebit r a te 1 1 0 0 x bit r a te bit r a te
146 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary a repeated s tart condition is gener a ted by writing the following v a l u e to ss con: after a repe a ted s tart condition (st a t u s 10h) the two-wire s eri a l interf a ce c a n a ccess the s a me sl a ve a g a in, or a new sl a ve witho u t tr a nsmitting a s top condition. repe a ted s tart en a bles the m a ster to switch between sl a ves, m a ster tr a nsmitter mode a nd m a ster receiver mode witho u t losing control of the b u s. . ss con cr2 ss ie s ta s to s i aa cr1 cr0 v a l u ebit r a te 1 0 1 0 x bit r a te bit r a te ss con cr2 ss ie s ta s to s i aa cr1 cr0 v a l u ebit r a te 1 1 0 0 x bit r a te bit r a te table 19-6. s t a t u s codes for m a ster tr a nsmitter mode status code (sscs) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from ssdat to sscon sta sto si aa 0x0 8 a s tart condition h a s been tr a nsmitted lo a d s la+w 0 0 1 x s la+w will be tr a nsmitted; ack or not ack will be received 10h a repe a ted s ta rt condition h a s been tr a nsmitted lo a d s la+w 0 0 1 x s la+w will be tr a nsmitted; ack or not ack will be received lo a d s la+r 0 0 1 x s la+r will be tr a nsmitted; logic will switch to m a ster receiver mode 1 8 h s la+w h a s been tr a nsmitted; ack h a s been received lo a d d a t a byte 0 0 1 x d a t a byte will be tr a nsmitted a nd ack or not ack will be received no a ction 1 0 1 x repe a ted s tart will be tr a nsmitted no a ction 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset no a ction 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset 20h s la+w h a s been tr a nsmitted; not ack h a s been received lo a d d a t a byte 0 0 1 x d a t a byte will be tr a nsmitted a nd ack or not ack will be received no a ction 1 0 1 x repe a ted s tart will be tr a nsmitted no a ction 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset no a ction 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset 2 8 h d a t a byte h a s been tr a nsmitted; ack h a s been received lo a d d a t a byte 0 0 1 x d a t a byte will be tr a nsmitted a nd ack or not ack will be received no a ction 1 0 1 x repe a ted s tart will be tr a nsmitted no a ction 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset no a ction 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset
147 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.6.2 master receiver mode in the m a ster receiver mode, a n u mber of d a t a bytes a re received from a sl a ve tr a nsmitter. in order to enter a m a ster mode, a s tart condition m u st be tr a nsmitted. the form a t of the follow- ing a ddress p a cket determines whether m a ster tr a nsmitter or m a ster receiver mode is to be entered. if s la+w is tr a nsmitted, mt mode is entered, if s la+r is tr a nsmitted, mr mode is entered. ss ie m u st be written to one to en a ble the two-wire s eri a l interf a ce, s ta m u st be written to one to tr a nsmit a s tart condition a nd s i m u st be cle a red. the twi will then test the two-wire s eri a l b u s a nd gener a te a s tart condition a s soon a s the b u s becomes free. after a s tart condition h a s been tr a nsmitted, the s i fl a g is set by h a rdw a re, a nd the st a t u s code in ss c s will be 0 8 h (see t a ble 19-7 ). in order to enter mr mode, s la+r m u st be tr a nsmitted. this is done by writing s la+r to ss dat. there a fter the s i bit sho u ld be cle a red to contin u e the tr a nsfer. when s la+r h a s been tr a nsmitted a nd a n a cknowledgment bit h a s been received, s i is set a g a in a nd a n u mber of st a t u s codes in ss c s a re possible. possible st a t u s codes in m a ster mode a re 3 8 h, 40h or 4 8 h. the a ppropri a te a ction to be t a ken for e a ch of these st a t u s codes is det a iled in t a ble 19-7 . received d a t a c a n be re a d from the ss dat register when the s i fl a g is set high by h a rdw a re. this scheme is repe a ted u ntil the l a st byte h a s been received. after the l a st byte h a s been received, the mr sho u ld inform the s t by sending a nack a fter the l a st received d a t a byte. the tr a nsfer is ended by gener a ting a s top condition or a repe a ted s tart condition. 30h d a t a byte h a s been tr a nsmitted; not ack h a s been received lo a d d a t a byte 0 0 1 x d a t a byte will be tr a nsmitted a nd ack or not ack will be received no a ction 1 0 1 x repe a ted s tart will be tr a nsmitted no a ction 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset no a ction 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset 3 8 h arbitr a tion lost in s la+w or d a t a bytes no a ction 0 0 1 x tw o - w i r e s eri a l b u s will be rele a sed a nd not a ddressed sl a ve mode entered no a ction 1 0 1 x a s tart condition will be tr a nsmitted when the b u s becomes free table 19-6. s t a t u s codes for m a ster tr a nsmitter mode
148 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 19-11. form a t a nd s t a tes in m a ster tr a nsmitter mode s sla w a data a p 08h 18h 28h r sla w 10h ap 20h p 3 0h a or a 3 8h a other ma s ter continue s a or a 3 8h other ma s ter continue s r a 68h other ma s ter continue s 78h b0h to corre s ponding s tate s in s lave mode mt mr succe ss full tran s mi ss ion to a s lave receiver next tran s fer s tarted with a repeated s tart condition not acknowledge received after the s lave addre ss not acknowledge received after a data b yte ar b itration lo s t in s lave addre ss or data b yte ar b itration lo s t and addre ss ed a s s lave data a n from ma s ter to s lave from s lave to ma s ter any num b er of data b yte s and their a ss ociated acknowledge b it s thi s num b er (contained in twsr) corre s pond s to a defined s tate of the two-wire serial bu s . the pre s caler b it s are zero or ma s ked to zero s
149 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 19-7. s t a t u s codes for m a ster receiver mode status code (sscs) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from ssdat to sscon sta sto si aa 0 8 h a s tart condition h a s been tr a nsmitted lo a d s la+r 0 0 1 x s la+r will be tr a nsmitted; ack or not ack will be received 10h a repe a ted s ta rt condition h a s been tr a nsmitted lo a d s la+r 0 0 1 x s la+r will be tr a nsmitted; ack or not ack will be received lo a d s la+w 0 0 1 x s la+w will be tr a nsmitted; logic will switch to m a ster tr a nsmitter mode 3 8 h arbitr a tion lost in s la+r or not ack bit no a ction 0 0 1 x tw o - w i r e s eri a l b u s will be rele a sed a nd not a ddressed s l a ve mode will be entered no a ction 1 0 1 x a s tart condition will be tr a nsmitted when the b u s becomes free 40h s la+r h a s been tr a nsmitted; ack h a s been received no a ction 0 0 1 0 d a t a byte will be received a nd not ack will be ret u rned no a ction 0 0 1 1 d a t a byte will be received a nd ack will be ret u rned 4 8 h s la+r h a s been tr a nsmitted; not ack h a s been received no a ction 1 0 1 x repe a ted s tart will be tr a nsmitted no a ction 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset no a ction 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset 50h d a t a byte h a s been received; ack h a s been ret u rned re a d d a t a byte 0 0 1 0 d a t a byte will be received a nd not ack will be ret u rned re a d d a t a byte 0 0 1 1 d a t a byte will be received a nd ack will be ret u rned 5 8 h d a t a byte h a s been received; not ack h a s been ret u rned re a d d a t a byte 1 0 1 x repe a ted s tart will be tr a nsmitted re a d d a t a byte 0 1 1 x s top condition will be tr a nsmitted a nd s to fl a g will be reset re a d d a t a byte 1 1 1 x s top condition followed by a s tart condition will be tr a nsmitted a nd s to fl a g will be reset
150 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 19-12. form a t a nd s t a tes in m a ster receiver mode 19.6.3 slave receiver mode in the s l a ve receiver mode, a n u mber of d a t a bytes a re received from a m a ster tr a nsmitter. to initi a te the s l a ve receiver mode, ss adr a nd ss con m u st be initi a lized a s follows: the u pper seven bits a re the a ddress to which the two-wire s eri a l interf a ce will respond when a ddressed by a m a ster. if the l s b is set, the twi will respond to the gener a l c a ll a ddress (00h), otherwise it will ignore the gener a l c a ll a ddress.: s sla r a data a 08h 40h 50h sla r 10h ap 48h a or a 3 8h other ma s ter continue s 3 8h other ma s ter continue s w a 68h other ma s ter continue s 78h b0h to corre s ponding s tate s in s lave mode mr mt succe ss full reception from a s lave receiver next tran s fer s tarted with a repeated s tart condition not acknowledge received after the s lave addre ss ar b itration lo s t in s lave addre ss or data b yte ar b itration lo s t and addre ss ed a s s lave data a n from ma s ter to s lave from s lave to ma s ter any num b er of data b yte s and their a ss ociated acknowledge b it s thi s num b er (contained in twsr) corre s pond s to a defined s tate of the two-wire serial bu s . the pre s caler b it s are zero or ma s ked to zero p data a 58h a r s ss adr s 6 s a5 s a4 s a3 s a2 s a1 s a0 gc v a l u e device?s own s l a ve address x ss con cr2 ss ie s ta s to s i aa cr1 cr0 v a l u e x10001xx
151 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ss ie m u st be written to one to en a ble the twi. the aa bit m u st be written to one to en a ble the a cknowledgment of the device?s own sl a ve a ddress or the gener a l c a ll a ddress. s ta a nd s to m u st be written to zero. when ss adr a nd ss con h a ve been initi a lized, the twi w a its u ntil it is a ddressed by its own sl a ve a ddress (or the gener a l c a ll a ddress if en a bled) followed by the d a t a direction bit. if the direction bit is ?0? (write), the twi will oper a te in s r mode, otherwise s t mode is entered. after its own sl a ve a ddress a nd the write bit h a ve been received, the s i fl a g is set a nd a v a lid st a t u s code c a n be re a d from ss c s . the st a t u s code is u sed to determine the a ppropri a te softw a re a ction. the a ppropri a te a ction to be t a ken for e a ch st a t u s code is det a iled in t a ble 19- 8 . the s l a ve receiver mode m a y a lso be entered if a rbitr a tion is lost while the twi is in the m a ster mode (see st a tes 6 8 h a nd 7 8 h). if the aa bit is reset d u ring a tr a nsfer, the twi will ret u rn a ?not acknowledge? (?1?) to s da a fter the next received d a t a byte. this c a n be u sed to indic a te th a t the sl a ve is not a ble to receive a ny more bytes. while aa is zero, the twi does not a cknowledge its own sl a ve a ddress. however, the two-wire s eri a l b u s is still monitored a nd a ddress recognition m a y res u me a t a ny time by setting aa. this implies th a t the aa bit m a y be u sed to tempor a rily isol a te the twi from the two- wire s eri a l b u s. . table 19-8. s t a t u s codes for s l a ve receiver mode status code (sscs) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from ssdat to sscon sta sto si aa 60h own s la+w h a s been received; ack h a s been ret u rned no a ction x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned no a ction x 0 1 1 d a t a byte will be received a nd ack will be ret u rned 6 8 h arbitr a tion lost in s la+r/w a s m a ster; own s la+w h a s been received; ack h a s been ret u rned no a ction x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned no a ction x 0 1 1 d a t a byte will be received a nd ack will be ret u rned 70h gener a l c a ll a ddress h a s been received; ack h a s been ret u rned no a ction x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned no a ction x 0 1 1 d a t a byte will be received a nd ack will be ret u rned 7 8 h arbitr a tion lost in s la+r/w a s m a ster; gener a l c a ll a ddress h a s been received; ack h a s been ret u rned no a ction x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned no a ction x 0 1 1 d a t a byte will be received a nd ack will be ret u rned 8 0h previo u sly a ddressed with own s la+w; d a t a h a s been received; ack h a s been ret u rned re a d d a t a byte x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned re a d d a t a byte x 0 1 1 d a t a byte will be received a nd ack will be ret u rned
152 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 88 h previo u sly a ddressed with own s la+w; d a t a h a s been received; not ack h a s been ret u rned re a d d a t a byte 0 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca re a d d a t a byte 0 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1? re a d d a t a byte 1 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will be tr a nsmitted when the b u s becomes free re a d d a t a byte 1 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1?; a s tart condition will be tr a nsmitted when the b u s becomes free 90h previo u sly a ddressed with gener a l c a ll; d a t a h a s been received; ack h a s been ret u rned re a d d a t a byte x 0 1 0 d a t a byte will be received a nd not ack will be ret u rned re a d d a t a byte x 0 1 1 d a t a byte will be received a nd ack will be ret u rned 9 8 h previo u sly a ddressed with gener a l c a ll; d a t a h a s been received; not ack h a s been ret u rned re a d d a t a byte 0 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca re a d d a t a byte 0 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1? re a d d a t a byte 1 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will be tr a nsmitted when the b u s becomes free re a d d a t a byte 1 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1?; a s tart condition will be tr a nsmitted when the b u s becomes free a0h a s top condition or repe a ted s tart condition h a s been received while still a ddressed a s sl a ve no action 0 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca no action 0 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1? no action 1 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will be tr a nsmitted when the b u s becomes free no action 1 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1?; a s tart condition will be tr a nsmitted when the b u s becomes free table 19-8. s t a t u s codes for s l a ve receiver mode
153 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 19-13. form a t a nd s t a tes in s l a ve receiver mode s sla w a data a 60h 80h 88h a 68h reception of the own s lave addre ss and one or more data b yte s . all are acknowledged la s t data b yte received i s not acknowledged ar b itration lo s t a s ma s ter and addre ss ed a s s lave reception of the general call addre ss and one or more data b yte s la s t data b yte received i s not acknowledged n from ma s ter to s lave from s lave to ma s ter any num b er of data b yte s and their a ss ociated acknowledge b it s thi s num b er (contained in twsr) corre s pond s to a defined s tate of the two-wire serial bu s . the pre s caler b it s are zero or ma s ked to zero p or s data a 80h a0h p or s a a data a 70h 90h 98h a 78h p or s data a 90h a0h p or s a general call ar b itration lo s t a s ma s ter and addre ss ed a s s lave b y general call data a
154 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 19.6.4 slave transmitter mode in the s l a ve tr a nsmitter mode, a n u mber of d a t a bytes a re tr a nsmitted to a m a ster receiver. to initi a te the s l a ve tr a nsmitter mode, u pper 7 bits of ss adr m u st be initi a lized with the a ddress to which the two-wire s eri a l interf a ce will respond when a ddressed by a m a ster. if the l s b is set, the twi will respond to the gener a l c a ll a ddress (00h), otherwise it will ignore the gener a l c a ll a ddress. ss ie m u st be written to one to en a ble the twi. the aa bit m u st be written to one to en a ble the a cknowledgment of the device?s own sl a ve a ddress or the gener a l c a ll a ddress. s ta a nd s to m u st be written to zero. when ss adr a nd ss con h a ve been initi a lized, the twi w a its u ntil it is a ddressed by its own sl a ve a ddress (or the gener a l c a ll a ddress if en a bled) followed by the d a t a direction bit. if the direction bit is ?1? (re a d), the twi will oper a te in s t mode, otherwise s r mode is entered. after its own sl a ve a ddress a nd the write bit h a ve been received, the twint fl a g is set a nd a v a lid st a t u s code c a n be re a d from ss c s . the st a t u s code is u sed to determine the a ppropri a te soft- w a re a ction. the a ppropri a te a ction to be t a ken for e a ch st a t u s code is det a iled in t a ble 19-9 . the s l a ve tr a nsmitter mode m a y a lso be entered if a rbitr a tion is lost while the twi is in the m a ster mode (see st a te b0h). if the aa bit is written to zero d u ring a tr a nsfer, the twi will tr a nsmit the l a st byte of the tr a nsfer. s t a te c0h or st a te c 8 h will be entered, dependi ng on whether the m a ster receiver tr a nsmits a nack or ack a fter the fin a l byte. the twi is switched to the not a ddressed s l a ve mode, a nd will ignore the m a ster if it contin u es the tr a nsfer. th u s the m a ster receiver receives a ll ?1s? a s seri a l d a t a . s t a te c 8 h is entered if the m a ster dem a nds a ddition a l d a t a bytes (by tr a nsmitting ack), even tho u gh the sl a ve h a s tr a nsmitted the l a st byte (aa zero a nd expecting nack from the m a ster). while aa is zero, the twi does not respond to its own sl a ve a ddress. however, the two-wire s eri a l b u s is still monitored a nd a ddress recognition m a y res u me a t a ny time by set- ting aa. this implies th a t the aa bit m a y be u sed to tempor a rily isol a te the twi from the two- wire s eri a l b u s. figure 19-14. form a t a nd s t a tes in s l a ve tr a nsmitter mode s sla r a data a a8h b8h a b0h reception of the own s lave addre ss and one or more data b yte s la s t data b yte tran s mitted. switched to not addre ss ed s lave (twea = '0') ar b itration lo s t a s ma s ter and addre ss ed a s s lave n from ma s ter to s lave from s lave to ma s ter any num b er of data b yte s and their a ss ociated acknowledge b it s thi s num b er (contained in twsr) corre s pond s to a defined s tate of the two-wire serial bu s . the pre s caler b it s are zero or ma s ked to zero p or s data c0h data a a c8h p or s all 1' s a
155 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary . 19.6.5 miscellaneous states there a re two st a t u s codes th a t do not correspond to a defined twi st a te, see t a ble 19-10 . s t a t u s f 8 h indic a tes th a t no relev a nt inform a tion is a v a il a ble bec au se the s i fl a g is not set. this occ u rs between other st a tes, a nd when the twi is not involved in a seri a l tr a nsfer. s t a t u s 00h indic a tes th a t a b u s error h a s occ u rred d u ring a two-wire s eri a l b u s tr a nsfer. a b u s error occ u rs when a s tart or s top condition occ u rs a t a n illeg a l position in the form a t fr a me. table 19-9. s t a t u s codes for s l a ve tr a nsmitter mode status code (sscs) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from ssdat to sscon sta sto si aa a 8 h own s la+r h a s been received; ack h a s been ret u rned lo a d d a t a byte x 0 1 0 l a st d a t a byte will be tr a nsmitted a nd not ack sho u ld be received lo a d d a t a byte x 0 1 1 d a t a byte will be tr a nsmitted a nd ack sho u ld be received b0h arbitr a tion lost in s la+r/w a s m a ster; own s la+r h a s been received; ack h a s been ret u rned lo a d d a t a byte x 0 1 0 l a st d a t a byte will be tr a nsmitted a nd not ack sho u ld be received lo a d d a t a byte x 0 1 1 d a t a byte will be tr a nsmitted a nd ack sho u ld be received b 8 h d a t a byte in ss dat h a s been tr a nsmitted; ack h a s been received lo a d d a t a byte x 0 1 0 l a st d a t a byte will be tr a nsmitted a nd not ack sho u ld be received lo a d d a t a byte x 0 1 1 d a t a byte will be tr a nsmitted a nd ack sho u ld be received c0h d a t a byte in ss dat h a s been tr a nsmitted; not ack h a s been received no a ction 0 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca no a ction 0 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1? no a ction 1 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will be tr a nsmitted when the b u s becomes free no a ction 1 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1?; a s tart condition will be tr a nsmitted when the b u s becomes free c 8 h l a st d a t a byte in ss dat h a s been tr a nsmitted (aa = ?0?); ack h a s been received no a ction 0 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca no a ction 0 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1? no a ction 1 0 1 0 s witched to the not a ddressed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will be tr a nsmitted when the b u s becomes free no a ction 1 0 1 1 s witched to the not a ddressed s l a ve mode; own s la will be recognized; gca will be recognized if gc = ?1?; a s tart condition will be tr a nsmitted when the b u s becomes free
156 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ex a mples of s u ch illeg a l positions a re d u ring the seri a l tr a nsfer of a n a ddress byte, a d a t a byte, or a n a cknowledge bit. when a b u s error occ u rs, s i is set. to recover from a b u s error, the s to fl a g m u st set a nd s i m u st be cle a red. this c au ses the twi to enter the not a ddressed s l a ve mode a nd to cle a r the s to fl a g (no other bits in ss con a re a ffected). the s da a nd s cl lines a re rele a sed, a nd no s top condition is tr a nsmitted. 19.6.6 combining several twi modes in some c a ses, sever a l twi modes m u st be combined in order to complete the desired a ction. consider for ex a mple re a ding d a t a from a seri a l eeprom. typic a lly, s u ch a tr a nsfer involves the following steps: 1. the tr a nsfer m u st be initi a ted. 2. the eeprom m u st be instr u cted wh a t loc a tion sho u ld be re a d. 3. the re a ding m u st be performed. 4. the tr a nsfer m u st be finished. note th a t d a t a is tr a nsmitted both from m a ster to s l a ve a nd vice vers a . the m a ster m u st instr u ct the s l a ve wh a t loc a tion it w a nts to re a d, req u iring the u se of the mt mode. su bseq u ently, d a t a m u st be re a d from the s l a ve, implying the u se of the mr mode. th u s, the tr a nsfer direction m u st be ch a nged. the m a ster m u st keep control of the b u s d u ring a ll these steps, a nd the steps sho u ld be c a rried o u t a s a n a tomic oper a tion. if this principle is viol a ted in a m u lti-m a ster sys- tem, a nother m a ster c a n a lter the d a t a pointer in the eeprom between steps 2 a nd 3, a nd the m a ster will re a d the wrong d a t a loc a tion. su ch a ch a nge in tr a nsfer direction is a ccomplished by tr a nsmitting a repeated s tart between the tr a nsmission of the a ddress byte a nd reception of the d a t a . after a repeated s tart, the m a ster keeps ownership of the b u s. the following fig u re shows the flow in this tr a nsfer. figure 19-15. combining s ever a l twi modes to access a s eri a l eeprom table 19-10. miscell a neo u s s t a tes status code (sscs) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from ssdat to sscon sta sto si aa f 8 h no relev a nt st a te inform a tion a v a il a ble; s i = ?0? no a ction no a ction w a it or proceed c u rrent tr a nsfer 00h b u s error d u e to a n illeg a l s ta rt o r s top condition no a ction 0 1 1 x only the intern a l h a rdw a re is a ffected, no s top condition is sent on the b u s. in a ll c a ses, the b u s is rele a sed a nd s to is cle a red. m a ster tr a nsmitter m a ster receiver s = s tart rs = repeated s tart p = s top tr a nsmitted from m a ster to sl a ve tr a nsmitted from sl a ve to m a ster s s la+w a addre ss a rs s la+r a data a p
157 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 20. dual analog comparators the at 8 9lp51rb2/rc2/ic2 provides two a n a log comp a r a tors. the a n a log comp a r a tors h a ve the following fe a t u res: ? intern a l 3-level volt a ge reference (1.125v, 1.25v, 1.375v) ?fo u r s h a red an a log inp u t ch a nnels ? config u re a s m u ltiple inp u t window comp a r a tor ? s elect a ble interr u pt conditions ? high- or low-level ? rising- or f a lling-edge ?o u tp u t toggle ?h a rdw a re debo u ncing modes figure 20-1. d ua l comp a r a tor block di a gr a m a block di a gr a m of the d ua l a n a log comp a r a tors with relev a nt connections is shown in fig u re 20-1 . inp u t options a llow the comp a r a tors to f u nction in a n u mber of different config u r a tions a s shown in fig u re 20-4 . comp a r a tor oper a tion is s u ch th a t the o u tp u t is a logic ?1? when the posi- tive inp u t is gre a ter th a n the neg a tive inp u t. otherwise the o u tp u t is a zero. s etting the cena (ac s ra.3) a nd cenb (ac s rb.3) bits en a ble comp a r a tor a a nd b respectively. the u ser m u st a lso set the cona (ac s ra.5) or conb (ac s rb.5) bits to connect the comp a r a tor inp u ts before u sing a comp a r a tor. when a comp a r a tor is first en a bled, the comp a r a tor o u tp u t a nd inter- r u pt fl a g a re not g ua r a nteed to be st a ble for 10 s. the corresponding comp a r a tor interr u pt sho u ld not be en a bled d u ring th a t time, a nd the comp a r a tor interr u pt fl a g m u st be cle a red before the interr u pt is en a bled in order to prevent a n immedi a te interr u pt service. before en a bling the comp a r a tors, the a n a log inp u ts sho u ld be trist a ted by p u tting p2.4, p2.5, p2.6 a nd p2.7 into inp u t-only mode. s ee ?port an a log f u nctions? on p a ge 72 . it is not possible to u se the an a log comp a r a tors with extern a l progr a m memory or extern a l d a t a memory with 16- bit a ddresses (movx @dptr) since these f u nctions req u ire the u se of port 2 for a ddressing. a b (p2.5) ain1 (p2.6) ain2 (p2.4) ain0 (p2.7) ain 3 11 10 01 00 11 10 01 00 rfb1 rfb0 rfa1 rfa0 11 10 01 00 11 10 01 00 csb0 csb1 csa0 csa1 cmpb cmpa cmb0 cmb1 cmb2 cma0 cma1 cma2 cfb cfa ecmp interrupt v aref v aref- v aref+
158 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary e a ch comp a r a tor m a y be config u red to c au se a n interr u pt u nder a v a riety of o u tp u t v a l u e condi- tions by setting the cm x 2-0 bits in ac s r x ( s ee t a ble 20-1 or t a ble 20-2 ). the comp a r a tor interr u pt fl a gs cf x in ac s r x a re set whenever the comp a r a tor o u tp u ts m a tch the conditions specified by cm x 2-0. the fl a gs m a y be polled by softw a re or m a y be u sed to gener a te a n inter- r u pt a nd m u st be cle a red by softw a re. both comp a r a tors sh a re a common interr u pt vector. if both comp a r a tors a re en a bled, the u ser needs to re a d the fl a gs a fter entering the interr u pt ser- vice ro u tine to determine which comp a r a tor c au sed the interr u pt. the cc s 1-0 bits in aref ( t a ble 20-3 ) control when the comp a r a tor interr u pts s a mple the com- p a r a tor o u tp u ts. norm a lly the o u tp u ts a re s a mpled every clock system; however, the o u tp u ts m a y a lso be s a mpled whenever timer 0, timer 1 or timer 2 overflows. these settings a llow the comp a r a tors to be s a mpled a t a specific time or to red u ce the n u mber of comp a r a tor events seen by the system when u sing level sensitive modes. the r a w v a l u e of the comp a r a tor o u tp u ts c a n a lw a ys be re a d from the cmpa a nd cmpb bits in aref. the comp a r a tors will contin u e to f u nction d u ring idle mode. if this is not the desired beh a vior, the comp a r a tors sho u ld be dis a bled before entering idle. the comp a r a tors a re a lw a ys dis a bled d u ring power-down mode. 20.1 analog input muxes the positive inp u t termin a l of e a ch comp a r a tor m a y be connected to a ny of the fo u r a n a log inp u t pins by ch a nging the c s a 1-0 or c s b 1-0 bits in ac s ra a nd ac s rb. when ch a nging the a n a log inp u t pins, the comp a r a tor m u st be disconnected from its inp u ts by cle a ring the cona or conb bits. the connection is restored by setting the bits a g a in a fter the m u xes h a ve been modified. clr ec ; disable comparator interrupts anl acsra, #0dfh ; clear cona to disconnect comp a ... ; modify csa or rfa bits orl acsra, #020h ; set cona to connect comp a anl acsra, #0efh ; clear any spurious interrupt setb ec ; re-enable comparator interrupts the corresponding comp a r a tor interr u pt sho u ld not be en a bled while the inp u ts a re being ch a nged, a nd the comp a r a tor interr u pt fl a g m u st be cle a red before the interr u pt is re-en a bled in order to prevent a n u nintention a l interr u pt req u est. the eq u iv a lent model for the a n a log inp u t circ u itry is ill u str a ted in fig u re 21-2 . an a n a log so u rce a pplied to ainn is s u bjected to the pin c a p a cit a nce a nd inp u t le a k a ge of th a t pin, reg a rdless of whether th a t ch a nnel is selected a s inp u t to the comp a r a tor. when the ch a nnel is selected, the so u rce m u st drive the inp u t c a p a cit a nce of the comp a r a tor thro u gh the series resist a nce (com- bined resist a nce in the inp u t p a th). figure 20-2. eq u iv a lent an a log inp u t model ainn c cmp < 0. 3 pf r in = 10 k c pin = 10 pf r mux = 10 k
159 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 20.2 internal reference voltage the neg a tive inp u t termin a l of e a ch comp a r a tor m a y be connected to a n intern a l volt a ge refer- ence by ch a nging the rfb 1-0 or rfa 1-0 bits in aref. the intern a l reference volt a ge, v aref , is set to 1.25 v 5%. the volt a ge reference a lso provides two a ddition a l volt a ge levels a pproxi- m a tely 125 mv a bove a nd below v aref . these levels m a y be u sed to config u re the comp a r a tors a s a n intern a lly referenced window comp a r a tor with u p to fo u r inp u t ch a nnels. ch a nging the ref- erence inp u t m u st follow the s a me ro u tine u sed for ch a nging the positive inp u t a s described in ?an a log inp u t m u xes? a bove. 20.3 comparator interrupt debouncing the comp a r a tor o u tp u t is norm a lly s a mpled every clock cycle. the conditions on the a n a log inp u ts m a y be s u ch th a t the comp a r a tor o u tp u t will toggle excessively. this is especi a lly tr u e if a pplying slow moving a n a log inp u ts. three debo u ncing modes a re provided to filter o u t this noise for edge-triggered interr u pts. in debo u ncing mode, the comp a r a tor u ses timer 1 to mod u - l a te its s a mpling time when c x c 1-0 = 00b. when a relev a nt tr a nsition occ u rs, the comp a r a tor w a its u ntil two timer 1 overflows h a ve occ u rred before res a mpling the o u tp u t. if the new s a mple a grees with the expected v a l u e, cf x is set. otherwise, the event is ignored. the filter m a y be t u ned by a dj u sting the time-o u t period of timer 1. bec au se timer 1 is free r u nning, the debo u ncer m u st w a it for two overflows to g ua r a ntee th a t the s a mpling del a y is a t le a st 1 time-o u t period. therefore, a fter the initi a l edge event, the interr u pt m a y occ u r between 1 a nd 2 time-o u t periods l a ter. s ee fig u re 20-3 . when the comp a r a tor clock is provided by one of the timer over- flows, i.e. c x c 1-0 ! = 00b, a ny ch a nge in the comp a r a tor o u tp u t m u st be v a lid a fter 4 s a mples to be a ccepted a s a n edge event. figure 20-3. neg a tive edge with debo u ncing ex a mple when the comp a r a tor s a mpling clock is config u red for a timer overflow, timer 1 still controls the debo u ncing. the s a mpling clock will determine when the edge event occ u rs a nd the interr u pt will be v a lid a ted two timer 1 overflows a fter this event. when timer 1 is selected for the s a mpling clock, this me a ns the interr u pt will occ u r on the second overflow a fter the overflow th a t s a mpled desired event. comp a r a tor o u t timer 1 overflow cfx s t a rt s t a rt comp a re (rejected) comp a re ( a ccepted)
160 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 20-4. d ua l comp a r a tor config u r a tion ex a mples a. dual independent comparator s with external reference s + - a cmpa ain0 ain1 + - b cmpb ain 3 ain2 csa = 00 rfa = 00 csb = 11 rfb = 00 b . 3 -channel comparator with external reference + - a cmpa ain0 ain1 csa = 00/10/11 rfa = 00 ain2 ain 3 c. 4-channel comparator with internal reference + - a cmpa ain0 v aref csa = 00/01/10/11 rfa = 10 ain1 ain2 ain 3 d. 2-channel comparator with internal reference & comparator with external reference + - a cmpa ain0 v aref csa = 00/01 rfa = 10 ain1 + - b cmpb ain 3 ain2 csb = 11 rfb = 00 e. 2-channel comparator with external reference & comparator with internal reference + - a cmpa ain0 v aref csa = 00/10 rfa = 00 ain1 + - b cmpb ain2 ain 3 csb = 11 rfb = 10 + - b cmpb + - a cmpa ain1 ain2 ain0 ain 3 csa = csb = 00/11 rfa = rfb = 00 f. 2-channel window comparator with external reference + - b cmpb + - a cmpa ain 3 ain0 ain1 ain2 csa = csb = 00/01/10/11 rfa = 01 rfb = 11 g. 4-channel window comparator with internal reference v aref+ v aref-
161 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. cona m u st be cle a red to 0 before ch a nging c s a 1-0 . 2. debo u ncing modes req u ire the u se of timer 1 to gener a te the s a mpling del a y. table 20-1. ac s ra ? an a log comp a r a tor a control & s t a t u s register ac s ra = a3h reset v a l u e = 0000 0000b not bit address a ble c s a1 c s a0 cona cfa cena cma2 cma1 cma0 bit76543210 symbol function c s a 1-0 comparator a positive input channel select (1) csa1 csa0 a+ channel 00ain0 (p2.4) 01ain1 (p2.5) 10ain2 (p2.6) 11ain3 (p2.7) cona comparator a input connect when cona = 1 the a n a log inp u t pins a re connected to the comp a r a tor. when cona = 0 the a n a log inp u t pins a re disconnected from the comp a r a tor. cona m u st be cle a red to 0 before ch a nging c s a[1-0] or rfa[1-0]. cfa comparator a interrupt flag s et when the comp a r a tor o u tp u t meets the conditions specif ied by the cma [2-0] bits a nd cena is set. the fl a g m u st be cle a red by softw a re. the interr u pt m a y be en a bled/dis a bled by setting/cle a ring bit 6 of ie. cena comparator a enable s et this bit to en a ble the comp a r a tor. cle a ring this bit will force the comp a r a tor o u tp u t low a nd prevent f u rther events from setting cfa. when cena = 1 the a n a log inp u t pins, p2.4?p2.7, h a ve their digit a l inp u ts dis a bled if they a re config u red in inp u t-only mode. cma 2-0 comparator a interrupt mode cma2 cma1 cma0 interrupt mode 000neg a tive (low) level 001positive edge 0 1 0 toggle with debo u ncing (2) 0 1 1 positive edge with debo u ncing (2) 100neg a tive edge 101toggle 110neg a tive edge with debo u ncing (2) 1 1 1 positive (high) level
162 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. conb m u st be cle a red to 0 before ch a nging c s b 1-0 . 2. debo u ncing modes req u ire the u se of timer 1 to gener a te the s a mpling del a y. table 20-2. ac s rb ? an a log comp a r a tor b control & s t a t u s register ac s rb = abh reset v a l u e = 1100 0000b not bit address a ble c s b1 c s b0 conb cfb cenb cmb2 cmb1 cmb0 bit76543210 symbol function c s b 1-0 comparator b positive input channel select (1) csb1 csb0 b+ channel 00ain0 (p2.4) 01ain1 (p2.5) 10ain2 (p2.6) 11ain3 (p2.7) conb comparator b input connect when conb = 1 the a n a log inp u t pins a re connected to the comp a r a tor. when conb = 0 the a n a log inp u t pins a re disconnected from the comp a r a tor. conb m u st be cle a red to 0 before ch a nging c s b[1-0] or rfb[1-0]. cfb comparator b interrupt flag s et when the comp a r a tor o u tp u t meets the conditions specif ied by the cmb [2-0] bits a nd cenb is set. the fl a g m u st be cle a red by softw a re. the interr u pt m a y be en a bled/dis a bled by setting/cle a ring bit 6 of ie. cenb comparator b enable s et this bit to en a ble the comp a r a tor. cle a ring this bit will force the comp a r a tor o u tp u t low a nd prevent f u rther events from setting cfb. when cenb = 1 the a n a log inp u t pins, p2.4?p2.7, h a ve their digit a l inp u ts dis a bled if they a re config u red in inp u t-only mode. cmb 2-0 comparator b interrupt mode cmb2 cmb1 cmb0 interrupt mode 000neg a tive (low) level 001positive edge 0 1 0 toggle with debo u ncing (2) 0 1 1 positive edge with debo u ncing (2) 100neg a tive edge 101toggle 110neg a tive edge with debo u ncing (2) 1 1 1 positive (high) level
163 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. conb (ac s rb.5) m u st be cle a red to 0 before ch a nging rfb[1-0]. 2. cona (ac s ra.5) m u st be cle a red to 0 before ch a nging rfa[1-0]. table 20-3. aref ? an a log comp a r a tor reference control register aref = bdh reset v a l u e = 0000 0000b not bit address a ble cmpb cmpa rfb1 rfb0 cc s 1cc s 0rfa1rfa0 bit76543210 symbol function cmpb comparator b output. copy of comp a r a tor b r a w o u tp u t v a l u e s a mpled by the system clock. cmpa comparator a output copy of comp a r a tor a r a w o u tp u t v a l u e s a mpled by the system clock. rfb 1-0 comparator b negative input channel select (1) crf1 rfb0 b- channel 0 0 ain2 (p2.6) 0 0 intern a l v aref- ( ~ 1.125v) 0 1 intern a l v aref ( ~ 1.25v) 0 1 intern a l v aref+ ( ~ 1.375v) cc s 1-0 comparator clock select ccs1 ccs0 clock source 00 s ystem clock 0 0 timer 0 overflow 0 1 timer 1 overflow 0 1 timer 2 overflow rfa 1-0 comparator a negative input channel select (2) rfa1 rfa0 a- channel 0 0 ain1 (p2.5) 0 0 intern a l v aref- ( ~ 1.125v) 0 1 intern a l v aref ( ~ 1.25v) 0 1 intern a l v aref+ ( ~ 1.375v)
164 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 21. digital-to-analog/analog-to-digital converter the at 8 9lp51rb2/rc2/ic2 incl u des a 10-bit d a t a converter (dadc) with the following fe a t u res: ? digit a l-to-an a log (dac) or an a log-to-digit a l (adc) mode ? 10-bit resol u tion ? 6.5 s conversion time ?7 m u ltiplexed s ingle-ended ch a nnels or 3 differenti a l ch a nnels ? intern a l temper a t u re s ensor or su pply volt a ge ch a nnels ? s elect a ble 1.0v10% intern a l reference volt a ge ?option a l left-adj u st of conversion res u lts ? s ingle conversion or timer-triggered mode ? interr u pt on conversion complete the at 8 9lp51rb2/rc2/ic2 fe a t u res a 10-bit s u ccessive a pproxim a tion d a t a converter th a t f u nctions in either an a log-to-digit a l (adc) or digit a l-to-an a log (dac) mode. a block di a gr a m of the converter is shown in fig u re 21-1 . an 8 -ch a nnel an a log m u ltiplexer connects eight single- ended or fo u r differenti a l volt a ge inp u ts from the pins of port 0 to a s a mple- a nd-hold circ u it th a t in t u rn provides a n inp u t to the s u ccessive a pproxim a tion block. the sa mple- a nd-hold circ u it ens u res th a t the inp u t volt a ge to the adc is held a t a const a nt level d u ring conversion. the s ar block digitizes the a n a log volt a ge into a 10-bit v a l u e a ccessible thro u gh a d a t a register. the s ar block a lso oper a tes in reverse to gener a te a n a n a log volt a ge on port 2 from a 10-bit digit a l v a l u e. adc res u lts a re a v a il a ble in the dadl a nd dadh register p a ir. the adc res u lt sc a le is deter- mined by the reference volt a ge (v ref ) gener a ted either intern a lly from a 1.0v reference or extern a lly from v dd /2. the adc res u lts a re a lw a ys represented in signed 2?s complement form, with single-ended volt a ge ch a nnels referring to the level a bove or below v dd /2. the 10-bit res u lts m a y be right or left a dj u sted within the 16-bit register. the sign is extended thro u gh the 6 m s bs of right- a dj u sted res u lts a nd the 6 l s bs of left- a dj u sted res u lts a re zeroed. if only 8 -bit precision is req u ired, the u ser sho u ld select left- a dj u sted by setting ladj in dadc a nd re a d only the dadh register. ex a mple res u lts a re listed in t a ble 21-1 . the conversion form u l a s a re a s follows: conversion res u lts c a n be converted into u nsigned bin a ry by a dding 02h to dadh in right- a dj u sted mode or 8 0h to dadh in left- a dj u sted mode. when u sing the extern a l reference (v dd /2) in single-ended mode this is eq u iv a lent to: ( s ingled-ended) adc 511 v in v dd 2 ? () ? v ref ----------------------------------------- = (differenti a l) adc 511 v in+ v in- ? v ref ---------------------------- = (unsigned s ingled-ended) adc 1023 v in v dd ---------- - =
165 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary to convert the u nsigned bin a ry v a l u e b a ck to 2?s complement, s u btr a ct 02h from dadh in right- a dj u sted mode or 8 0h from dadh in left- a dj u sted mode. note th a t the dadh/dadl registers c a nnot be directly m a nip u l a ted a s they a re re a d-only in adc mode a nd write-only in dac mode. figure 21-1. dadc block di a gr a m 8-bit data bus 15 0 adc input select register (dadi) adc ctrl & status register (dadc) adc data register (dadh/dadl) acs2 dac adif acs1 acs0 ack0 ack1 ack2 diff 10-bit sar sample & hold internal 1.0v reference acon vdd p0.6 p0.5 p0.4 p0. 3 p0.2 p0.1 p0.0 iref + - channel selection prescaler gnd pos. input mux neg. input mux trigger select timer overflow s interrupt flag start vdd/2 da+ da- trg1 trg0 go adce ladj vref vin+ vin- r r vdd/2 iref 7r r vdd/8 vdd/8 temp
166 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 21.1 adc operation the adc converts a n a n a log inp u t volt a ge to a 10-bit signed digit a l v a l u e thro u gh s u ccessive a pproxim a tion. when diff (dadi.3) is zero, the adc oper a tes in single-ended mode a nd the inp u t volt a ge is the difference between the volt a ge a t the inp u t pin a nd v dd /2. in differenti a l mode (diff = 1) the inp u t volt a ge is the difference between the positive a nd neg a tive inp u t pins. the minim u m v a l u e represents zero difference a nd the m a xim u m v a l u es represent a difference of positive or neg a tive v ref min u s 1 l s b. the a n a log inp u t ch a nnel is selected by writing to the ac s bits in dadi. the first six port 0 inp u t pins c a n be selected a s single-ended inp u ts to the adc. three p a irs of port 0 pins c a n be selected a s differenti a l inp u ts.the acon bit (dadi.7) m u st be set to one to connect the inp u t pins to the adc. prior to ch a nging ac s , acon m u st be cle a red to zero. this ens u res th a t crosst a lk between ch a nnels is limited. acon m u st be set b a ck to one a fter ac s is u pd a ted. acon a nd ac s sho u ld not be ch a nged while a conversion is in progress. adc inp u t ch a nnels m u st h a ve their port pins config u red for inp u t-only mode. the at 8 9lp51rb2/rc2/ic2 a lso incl u des a n on-chip temper a t u re sensor a nd volt a ge s u pply ch a nnel. these fe a t u res a re a v a il- a ble when ac s =6. s ee s ection 21.2 . the eq u iv a lent model for the a n a log inp u t circ u itry is ill u str a ted in fig u re 21-2 . an a n a log so u rce a pplied to adcn is s u bjected to the pin c a p a cit a nce a nd inp u t le a k a ge of th a t pin, reg a rdless of whether th a t ch a nnel is selected a s inp u t to the adc. when the ch a nnel is selected, the so u rce m u st drive the s /h c a p a citor thro u gh the series resist a nce (combined resist a nce in the inp u t p a th). to a chieve 10-bit resol u tion the s /h c a p a citor m u st be ch a rged to within 1/2 l s b of the expected v a l u e within the 1 adc clock period s a mple time. high imped a nce so u rces m a y req u ire a red u ction in the adc clock freq u ency to a chieve f u ll resol u tion. figure 21-2. eq u iv a lent an a log inp u t model the adc is en a bled by setting the adce bit in dadc. s ome settling time is req u ired for the ref- erence circ u its to st a bilize a fter the adc is en a bled. the adc does not cons u me power when adce is cle a red, so it is recommended to switch off the adc before entering power s a ving modes. table 21-1. ex a mple adc conversion codes right adjust left adjust single-ended mode (v in ) differential mode (v in + ? v in -) 00 v dd /2 0 0100h 4000h v dd /2 + 1/2 x v ref 1/2 x v ref 01ffh 7fc0h v dd /2 + 511/512 x v ref 511/512 x v ref ff00h c000h v dd /2 ? 1/2 x v ref ?1/2 x v ref fe01h 8 040h v dd /2 ? 511/512 x v ref ?511/512 x v ref adcn c s/h = 2 pf r in = 10 k c pin = 10 pf r mux = 10 k
167 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary a timing di a gr a m of a n adc conversion is shown in fig u re 21-3 . the conversion req u ires 13 adc clock cycles to complete. the a n a log inp u t is s a mpled d u ring the third cycle of the conver- sion a nd is held const a nt for the rem a inder of the conversion. at the end of the conversion, the interr u pt fl a g, adif, is set a nd the res u lt is written to the d a t a registers. an a ddition a l 1 adc clock cycle a nd u p to 2 system clock cycles m a y be req u ired to synchronize adif with the rest of the system. the res u lts in dadh/dadl rem a in v a lid u ntil the next conversion completes. dadh a nd dadl a re re a d-only registers d u ring adc mode. figure 21-3. adc timing di a gr a m 21.2 temperature sensor adc inp u t ch a nnel 6 is not connected to a port pin. inste a d it h a s a connection to two intern a l speci a l f u nctions: a temper a t u re sensor a nd a volt a ge s u pply monitor. when ac s = 6 the iref bit in dadi selects between them, s u ch th a t iref = 0 selects the volt a ge s u pply ch a nnel a nd iref = 1 select the temper a t u re sensor ch a nnel. both these modes u se the intern a l 1.0v refer- ence for the f u ll sc a le a nd the neg a tive inp u t. the temper a t u re sensor o u tp u ts a volt a ge th a t is proportion a l to the a mbient oper a ting temper a t u re. the u nc a libr a ted o u tp u t is line a r a nd is s u it- a ble for rel a tive temper a t u re me a s u rements. the s u pply volt a ge ch a nnel is the device s u pply level divided-by- 8 . it c a n be u sed to find the a ct ua l oper a ting volt a ge of the device. the following conversion form u l a e a pply for temper a t u re sensor a nd s u pply monitor modes: 21.3 dac operation the dac converts a 10-bit signed digit a l v a l u e to a n a n a log o u tp u t volt a ge thro u gh s u ccessive a pproxim a tion. the dac a lw a ys oper a tes in differenti a l mode, o u tp u tting a volt a ge differenti a l between its positive (p2.2) a nd neg a tive (p2.3) o u tp u ts with a common mode of v dd /2. the min- im u m v a l u e represents zero difference a nd the m a xim u m v a l u es represent a difference of positive or neg a tive v ref min u s 1 l s b. the dac is en a bled by setting the adce a nd dac bits in dadc. s ome settling time is req u ired for the reference circ u its to st a bilize a fter the dac is en a bled. the dac does not h a ve m u ltiple 12 3 4 5 6 7 8 9 1011121 3 msb of re s ult lsb of re s ult adc clock go/bsy adif dadh dadl cycle num b er 12 one conver s ion next conver s ion 3 sample & hold initialize circuitry conver s ion complete initialize (temp s ensor) adc 511 v temp v ref ? v ref ------------------------------------ - = ( su pply volt a ge) adc 511 vdd 8 ? () v ref ? v ref ----------------------------------------------- - =
168 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary o u tp u t ch a nnels a nd the diff, acon a nd ac s bits h a ve no effect in dac mode. p2.2 a nd p2.3 a re au tom a tic a lly forced to inp u t-only mode while the dac is en a bled. a timing di a gr a m of a dac conversion is shown in fig u re 21-4 . the conversion req u ires 11 adc clock cycles to complete. constr u ction of the a n a log o u tp u t st a rts in the second cycle of the con- version a nd the dac will a llow the new v a l u e to prop a g a te to the o u tp u ts d u ring cycle 7, a fter the 5 m s bs a re complete. at the end of the conversion, the interr u pt fl a g is set. an a ddition a l 1 adc clock cycle a nd u p to 2 system clock cycles m a y be req u ired to synchronize adif with the rest of the system. the dadl a nd dadh registers hold the v a l u e to be o u tp u t a nd a re write-only d u ring dac mode. an intern a l b u ffer s a mples dadh/dadl a t the st a rt of the conversion a nd holds the v a l u e const a nt for the rem a inder of the conversion. on e system clock cycle is req u ired to tr a ns- fer the contents of dadh/dadl into the b u ffer a t the st a rt of the conversion a nd therefore the adc clock freq u ency m u st a lw a ys be eq ua l to or less th a n the system clock freq u ency d u ring dac mode to ens u re th a t the b u ffer is u pd a ted before the second cycle. figure 21-4. dac timing di a gr a m the eq u iv a lent model for the a n a log o u tp u t circ u itry is ill u str a ted in fig u re 21-5 . the series o u t- p u t resist a nce of the dac m u st drive the pin c a p a cit a nce a nd a ny extern a l lo a d on the pin. figure 21-5. eq u iv a lent an a log o u tp u t model 21.4 clock selection the dadc req u ires a clock of 2 mhz or less to a chieve f u ll resol u tion. by def au lt the dadc will u se a n intern a l 2 mhz clock gener a ted from the 8 mhz intern a l oscill a tor. the intern a l oscill a tor will be en a bled even if it is not s u pplying the system clock. this m a y res u lt in higher power con- s u mption. conversely, the dadc clock c a n be gener a ted directly from the system oscill a tor u sing a 7-bit presc a ler. the presc a ler o u tp u t is controlled by the ack bits in dadc a s shown in fig u re 21-6 . the presc a ler is independent of a ny x2 or ckrl division u sed for the cpu clock. 12 3 4567891011 msb of output lsb of output adc clock go/bsy adif dadh dadl cycle num b er 12 one conver s ion next conver s ion 3 begin output initialize circuitry conver s ion complete initialize dan v out r out = 100 k c pin = 10 pf av dd /2
169 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary in adc mode, there a re no req u irements on the clock freq u ency with respect to the system clock. the adc presc a ler selection is independent of the system clock divider a nd the adc m a y oper a te a t both higher or lower freq u encies th a n the cpu. however, in dac mode the adc clock freq u ency m u st not be higher th a n the cpu clock, incl u ding a ny clock division from the system clock. figure 21-6. dadc clock s election 21.5 starting a conversion s etting the go/b s y bit (dadc.6) when adce = 1 st a rts a single conversion in both adc a nd dac modes. the bit rem a ins set while the conver sion is in progress a nd is cle a red by h a rdw a re when the conversion completes. the adc ch a nnel sho u ld not be ch a nged while a conversion is in progress. altern a tively, a conversion c a n be st a rted au tom a tic a lly by v a rio u s timer so u rces. conversion trigger so u rces a re selected by the trg bits in dadi. a conversion is st a rted every time the selected timer overflows, a llowing for conversions to occ u r a t fixed interv a ls. the go/b s y bit will be set by h a rdw a re while the conversion is in progress. note th a t the timer overflow r a te m u st be slower th a n the conversion time. 21.6 noise considerations digit a l circ u itry inside a nd o u tside the device gener a tes emi which might a ffect the a cc u r a cy of a n a log me a s u rements. if conversion a cc u r a cy is critic a l, the noise level c a n be red u ced by a pplying the following techniq u es: ? keep a n a log sign a l p a ths a s short a s possible. m a ke s u re to r u n a n a log sign a ls tr a cks over a n a n a log gro u nd pl a ne, a nd keep them well a w a y from high-speed digit a l tr a cks. ?pl a ce the cpu in idle d u ring a conversion. for best res u lts, u se a timer to st a rt the conversion while cpu is a lre a dy in idle mode. ?if a ny port 0 pins a re u sed a s digit a l o u tp u ts, it is essenti a l th a t these do not switch while a conversion is in progress. 7-bit adc pre s caler adc clock s ource o s c ack0 ack1 ack2 ck/12 8 ck/2 ck/4 ck/ 8 ck/16 ck/32 ck/64 internal 8 mhz o s c 4
170 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 21.7 registers note: 1. f o s c is the freq u ency of the system clock oscill a tor so u rce before the x1/x2 a nd ckrl dividers. table 21-2. dadc ? dadc control register dadc = a4h reset v a l u e = 0000 0000b not bit address a ble adif go/b s y dac adce ladj ack2 ack1 ack0 bit76543210 symbol function adif adc interrupt flag s et by h a rdw a re when a conversion completes. cle a red by h a rdw a re when c a lling the interr u pt service ro u tine. go/b s y conversion start/busy flag in softw a re triggered mode, writing a 1 to this bit st a rts a conversion. the bit rem a ins high while the conversion is in progress a nd is cle a red by h a rdw a re when the conversion completes. in h a rdw a re triggered mode, this bit is set a nd cle a red by h a rdw a re to fl a g when the dadc is b u sy. dac digital-to-analog conversion enable s et to config u re the dadc in digit a l-to-an a log (dac) mode. cle a r to config u re the dadc in an a log-to-digit a l (adc) mode. adce dadc enable s et to en a ble the dadc. cle a r to dis a ble the dadc. ladj left adjust enable when cle a red, the adc res u lts a re right a dj u sted a nd the m s bs a re sign extended. when set, the adc res u lts a re left a dj u sted a nd the l s bs a re zeroed. ack 2-0 dadc clock select ack3 ack1 ack0 clock source (1) 000intern a l rc oscill a tor/4 (2mhz) 001f o s c /2 010f o s c /4 011f o s c / 8 100f o s c /16 101f o s c /32 110f o s c /64 111f o s c /12 8 table 21-3. dadi ? dadc inp u t control register dadi = a5h reset v a l u e = 0000 0000b not bit address a ble acon iref trg1 trg0 diff ac s 2ac s 1ac s 0 bit76543210
171 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: 1. v temp is provided by the temper a t u re sensor when iref = 1. otherwise v temp = vdd/ 8 when iref = 0. symbol function acon analog input connect when cle a red, the a n a log inp u ts a re disconnected from the adc. when set, the a n a log inp u ts selected by ac s 2-0 a re connected to the adc. acon m u st be zero when ch a nging the inp u t ch a nnel m u ltiplexor (ac s 2-0 ). iref internal reference enable when set, the dadc u ses the intern a l volt a ge reference. when cle a red the dadc u ses vdd for its reference. diff differential mode enable s et to config u re the adc in differenti a l mode. cle a r to config u re the adc in single-ended mode. trg 1-0 trigger select trg1 trg0 trigger 00 s oftw a re (go bit) 0 1 timer 0 overflow 1 0 timer 1 overflow 1 1 timer 2 overflow ac s 2-0 adc channel select diff acs2 acs1 acs0 v+ v- 0000p0.0vdd/2 0001p0.1vdd/2 0010p0.2vdd/2 0011p0.3vdd/2 0100p0.4vdd/2 0101p0.5vdd/2 0110v temp (1) v ref 0111p0.6vdd/2 1000p0.0p0.1 1001p0.2p0.3 1010p0.4p0.5 1011reserved 1 1 x x reserved table 21-4. dadl ? dadc d a t a low register dadl = ach reset v a l u e = 0000 0000b not bit address a ble adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 adc.1 adc.0 bit76543210
172 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: when ladj = 0, bits 7?0 of the adc res u lt a re fo u nd in bits 7?0 of dadl. when ladj = 1, bits 1?0 of the adc res u lt a re fo u nd in bits 7?6 of dadl. bits 5?0 a re cle a red to zero. note: when ladj = 0, bits 9? 8 of the adc res u lt a re fo u nd in bits 1?0 of dadh. bits 7?2 a re signed extended copies of bit 1. when ladj = 1, bits 9?2 of the adc res u lt a re fo u nd in bits 7?0 of dadh. table 21-5. dadh ? dadc d a t a high register dadh = adh reset v a l u e = 0000 0000b not bit address a ble adc.15 adc.14 adc.13 adc.12 adc.11 adc.10 adc.9 adc. 8 bit76543210
173 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22. instruction set summary the at 8 9lp51rb2/rc2/ic2 is f u lly bin a ry comp a tible with the 8 051 instr u ction set. in comp a ti- bility mode the at 8 9lp51rb2/rc2/ic2 h a s identic a l exec u tion time with at 8 9c51rb2/rc2/ic2 a nd other st a nd a rd 8 051s. the difference between the at 8 9lp51rb2/rc2/ic2 in f a st mode a nd the st a nd a rd 8 051 is the n u mber of cycles req u ired to exec u te a n instr u ction. f a st mode instr u ctions m a y t a ke 1 to 5 clock cycles to complete. the exec u tion times of most instr u ctions m a y be comp u ted u sing t a ble 22-1 . note th a t for the p u r- poses of this t a ble, a clock cycle is one period of the o u tp u t of the system clock divider. for f a st mode the divider def au lts to 1, so the clock cycle eq ua ls the oscill a tor period. for comp a tibility mode the divider def au lts to 2, so the clock cycle is twice the oscill a tor period, or conversely the clock co u nt is h a lf the n u mber of oscill a tor periods. table 22-1. instr u ction exec u tion times a nd exceptions (1) generic instruction types fast mode cycle count formula most a rithmetic, logic a l, bit a nd tr a nsfer instr u ctions # bytes br a nches a nd c a lls # bytes + 1 s ingle byte indirect (i.e. add a, @ri, etc.) 2 ret, reti 4 movc 3 movx 4 (3) mul 2 div 4 mac 9 inc dptr 2 arithmetic bytes clock cycles hex code compatibility fast add a, rn 1 6 1 2 8 -2f add a, direct 2 6 2 25 add a, @ri 1 6 2 26-27 add a, #d a t a 26 2 24 addc a, rn 1 6 1 3 8 -3f addc a, direct 2 6 2 35 addc a, @ri 1 6 2 36-37 addc a, #d a t a 26 2 34 s ubb a, rn 1 6 1 9 8 -9f s ubb a, direct 2 6 2 95 s ubb a, @ri 1 6 2 96-97 s ubb a, #d a t a 26 2 94 inc rn 1 6 1 0 8 -0f inc direct 2 6 2 05 inc @ri 1 6 2 06-07 inc a 2 6 2 04
174 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary dec rn 1 6 1 1 8 -1f dec direct 2 6 2 15 dec @ri 1 6 2 16-17 dec a 2 6 2 14 inc dptr 1 12 2 a3 inc /dptr (2) 21 8 3a5 a3 mul ab 1 24 2 a4 div ab 1 24 4 8 4 da a 1 6 1 d4 mac ab (2) 2? 9a5 a4 clr m (2) 2? 2a5 e4 a s r m (2) 2? 2a5 03 l s l m (2) 2? 2a5 23 logical bytes clock cycles hex code compatibility fast clr a 1 6 1 e4 cpl a 1 6 1 f4 anl a, rn 1 6 1 5 8 -5f anl a, direct 2 6 2 55 anl a, @ri 1 6 2 56-57 anl a, #d a t a 26 2 54 anl direct, a 2 6 2 52 anl direct, #d a t a 312 3 53 orl a, rn 1 6 1 4 8 -4f orl a, direct 2 6 2 45 orl a, @ri 1 6 2 46-47 orl a, #d a t a 26 2 44 orl direct, a 2 6 2 42 orl direct, #d a t a 312 3 43 xrl a, rn 1 6 1 6 8 -6f xrl a, direct 2 6 2 65 xrl a, @ri 1 6 2 66-67 xrl a, #d a t a 26 2 64 xrl direct, a 2 6 2 62 xrl direct, #d a t a 312 3 63 rl a 1 6 1 23 rlc a 1 6 1 33 rr a 1 6 1 03 rrc a 1 6 1 13 table 22-1. instr u ction exec u tion times a nd exceptions (1) (contin u ed)
175 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary s wap a 1 6 1 c4 data transfer bytes clock cycles hex code compatibility fast mov a, rn 1 6 1 e 8 -ef mov a, direct 2 6 2 e5 mov a, @ri 1 6 2 e6-e7 mov a, #d a t a 26 2 74 mov rn, a 1 6 1 f 8 -ff mov rn, direct 2 12 2 a 8 -af mov rn, #d a t a 26 27 8 -7f mov direct, a 2 6 2 f5 mov direct, rn 2 12 2 88 - 8 f mov direct, direct 3 12 3 8 5 mov direct, @ri 2 12 2 8 6- 8 7 mov direct, #d a t a 312 3 75 mov @ri, a 1 6 1 f6-f7 mov @ri, direct 2 12 2 a6-a7 mov @ri, #d a t a 2 6 2 76-77 mov dptr, #d a t a 16 3 12 3 90 mov /dptr, #d a t a 16 (2) 4? 4a5 90 movc a, @a+dptr 1 12 3 93 movc a, @a+/dptr (2) 2? 4a5 93 movc a, @a+pc 1 12 3 8 3 movx a, @ri 1 12 2 e2-e3 movx a, @dptr 1 12 (3) 4 (3) e0 movx a, @/dptr (2) 21 8 (3) 5 (3) a5 e0 movx @ri, a 1 12 2 f2-f3 movx @dptr, a 1 12 (3) 4 (3) f0 movx @/dptr, a (2) 21 8 (3) 5 (3) a5 f0 pu s h direct 2 12 2 c0 pop direct 2 12 2 d0 xch a, rn 1 6 1 c 8 -cf xch a, direct 2 6 2 c5 xch a, @ri 1 6 2 c6-c7 xchd a, @ri 1 6 2 d6-d7 bit operations bytes clock cycles hex code compatibility fast clr c 1 6 1 c3 clr bit 2 6 2 c2 table 22-1. instr u ction exec u tion times a nd exceptions (1) (contin u ed)
176 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. a clock cycle is one period of the o u tp u t of the system clock divider. for f a st mode the divider def au lts to 1, so the clock cycle eq ua ls the oscill a tor period. for comp a tibility mode the divider s etb c 1 6 1 d3 s etb bit 2 6 2 d2 cpl c 1 6 1 b3 cpl bit 2 6 2 b2 anl c, bit 2 12 2 8 2 anl c, bit 2 12 2 b0 orl c, bit 2 12 2 72 orl c, /bit 2 12 2 a0 mov c, bit 2 6 2 a2 mov bit, c 2 12 2 92 branching bytes clock cycles hex code compatibility fast jc rel 2 12 3 40 jnc rel 2 12 3 50 jb bit, rel 3 12 4 20 jnb bit, rel 3 12 4 30 jbc bit, rel 3 12 4 10 jz rel 2 12 3 60 jnz rel 2 12 3 70 s jmp rel 2 12 3 8 0 acall a ddr11 2 12 3 11,31,51,71,91, b1,d1,f1 lcall a ddr16 3 12 4 12 ret 1 12 4 22 reti 1 12 4 32 ajmp a ddr11 2 12 3 01,21,41,61, 8 1, a1,c1,e1 ljmp a ddr16 3 12 4 02 jmp @a+dptr 1 12 2 73 jmp @a+pc (2) 212 3 a573 cjne a, direct, rel 3 12 4 b5 cjne a, #d a t a , rel 3 12 4 b4 cjne rn, #d a t a , rel 3 12 4 b 8 -bf cjne @ri, #d a t a , rel 3 12 4 b6-b7 cjne a, @r0, rel (2) 31 8 4a5 b6 cjne a, @r1, rel (2) 31 8 4a5 b7 djnz rn, rel 2 12 3 d 8 -df djnz direct, rel 3 12 4 d5 nop 1 6 1 00 table 22-1. instr u ction exec u tion times a nd exceptions (1) (contin u ed)
177 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary def au lts to 2, so the clock cycle is twice the oscill a tor period, or conversely the clock co u nt is h a lf the n u mber of oscill a tor periods. 2. this esc a ped instr u ction is a n extension to the instr u ction set. 3. this is the minim u m time for movx with no w a it st a tes. in comp a tibility mode a n a ddition a l 24 clocks a re a dded for the w a it st a te. in f a st mode, 1 clock is a dded for e a ch w a it st a te (0?3). 22.1 instruction set extensions the following instr u ctions a re extensions to the st a nd a rd 8 051 instr u ction set th a t provide enh a nced c a p a bilities not fo u nd in st a nd a rd 8 051 devices. all extended instr u ctions st a rt with a n a5h esc a pe code. for this re a son r a ndom a5h reserved codes sho u ld not be pl a ced in the instr u ction stre a m even tho u gh other devices m a y h a ve tre a ted these a s nops. other at 8 9lp devices m a y not s u pport a ll of these instr u ctions. 22.1.1 asr m function: s hift mac acc u m u l a tor right arithmetic a lly description: the forty bits in the m register a re shifted one bit to the right. bit 39 ret a ins its v a l u e to preserve the sign of the v a l u e. no fl a gs a re a ffected. example: the m register holds the v a l u e 0c5b1a293 8 4h . the following instr u ction, a s r m le a ves the m register holding the v a l u e 0e2d 8 d149c2h. bytes: 2 cycles: 2 encoding: a5 00000011 operation: a s r (m n ) (m n + 1 ) n = 0 - 3 8 (m 39 ) (m 39 ) 22.1.2 break function: s oftw a re bre a kpoint (h a lt exec u tion) description: break tr a nsfers control from norm a l exec u tion to the on-chip deb u g (ocd) h a ndler if ocd is en a bled. the pc is left pointing to the following instr u ction. if ocd is dis a bled, break a cts a s a do u ble nop. no fl a gs a re a ffected. example: if on-chip deb u gging is a llowed, the following instr u ction, break will h a lt instr u ction exec u tion prior to the immedi a tely following instr u ction. if deb u gging is not a llowed, the break is tre a ted a s a do u ble nop. bytes: 2 cycles: 2 encoding: a5 00000000 operation: break (pc) (pc) + 2
178 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22.1.3 cjne a, @r i , rel function: comp a re a nd j u mp if not eq ua l description: cjne comp a res the m a gnit u des of the acc u m u l a tor a nd indirect ram loc a tion a nd br a nches if their v a l u es a re not eq ua l. the br a nch destin a tion is comp u ted by a dding the signed rel a tive-displ a cement in the l a st instr u ction byte to the pc, a fter incrementing the pc to the st a rt of the next instr u ction. the c a rry fl a g is set if the u nsigned integer v a l u e of acc is less th a n the u nsigned integer v a l u e of the indirect loc a tion; otherwise, the c a rry is cle a red. neither oper a nd is a ffected. example: the acc u m u l a tor cont a ins 34h. register 0 cont a ins 7 8 h a nd 7 8 h cont a ins 56h. the first instr u ction in the seq u ence, cjne a, @r0, not_eq ; . . . . . . ...... ...... ; acc = @r0. not_eq: jc req_low .. ;if acc< @r0. ; . . . . . . ...... ...... ;acc > @r0. sets the c a rry fl a g a nd br a nches to the instr u ction a t l a bel not_eq. by testing the c a rry fl a g, the second instr u ction determines whether acc is gre a ter or less th a n the loc a tion pointed to by r0. bytes: 2 cycles: 9 encoding: a5 1011011 i rel. a ddress operation: cjne (pc) (pc) + 3 if (a) ((r i )) then (pc) (pc) + rel a tive offset if (a) < ((r i )) then (c) 1 el s e (c) 0 22.1.4 clr m function: cle a r mac acc u m u l a tor description: clr m cle a rs the 40-bit m register. no fl a gs a re a ffected. example: the m registercont a ins 1234567 8 9ah. the following instr u ction, clr m le a ves the m register set to 0000000000h. bytes: 2 cycles: 2 encoding: a5 11100100 operation: jmp (m) 0
179 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22.1.5 inc /dptr function: increment altern a te d a t a pointer description: inc /dptr increments the u nselected 16-bit d a t a pointer by 1. a 16-bit increment (mod u lo 2 16 ) is performed, a nd a n overflow of the low-order byte of the d a t a pointer from 0ffh to 00h incr ements the high-order byte. no fl a gs a re a ffected. example: registers dp1h a nd dp1l cont a in 12h a nd 0feh, respectively, a nd dp s = 0. the following instr u ction seq u ence, inc /dptr inc /dptr inc /dptr ch a nges dp1h a nd dp1l to 13h a nd 01h. bytes: 2 cycles: 3 encoding: a5 10100011 operation: inc if (dp s ) = 0 then (dptr1) (dptr1) + 1 el s e (dptr0) (dptr0) + 1 22.1.6 jmp @a+pc function: j u mp indirect rel a tive to pc description: jmp @a+pc a dds the eight-bit u nsigned contents of the acc u m u l a tor to the progr a m co u nter, which is first incremented by two. this is the a ddress for s u bseq u ent instr u ction fetches. s ixteen-bit a ddition is performed (mod u lo 2 16 ): a c a rry-o u t from the low-order eight bits prop a g a tes thro u gh the higher-order bits. the acc u m u l a tor is not a ltered. no fl a gs a re a ffected. example: an even n u mber from 0 to 6 is in the acc u m u l a tor. the following seq u ence of instr u ctions br a nches to one of fo u r ajmp instr u ctions in a j u mp t a ble st a rting a t jmp_tbl. jmp @a + pc jmp_tbl: ajmp label0 ajmp label1 ajmp label2 ajmp label3 if the acc u m u l a tor eq ua ls 04h when st a rting this seq u ence, exec u tion j u mps to l a bel label2. bec au se ajmp is a 2-byte instr u ction, the j u mp instr u ctions st a rt a t every other a ddress. bytes: 2 cycles: 3 encoding: a5 01110011 operation: jmp (pc) (a) + (pc) + 2
180 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22.1.7 lsl m function: s hift mac acc u m u l a tor left logic a lly description: the forty bits in the m register a re shifted one bit to the left. bit 0 is cle a red. no fl a gs a re a ffected. example: the m register holds the v a l u e 0c5b1a293 8 4h. the following instr u ction, l s l m le a ves the m register holding the v a l u e 8 b6345270 8 h. bytes: 2 cycles: 2 encoding: a5 00100011 operation: l s l (m n+1 ) (m n ) n = 0 - 3 8 (m 0 ) 0 22.1.8 movc a, @a+/dptr function: move code byte rel a tive to altern a te d a t a pointer description: the movc instr u ctions lo a d the acc u m u l a tor with a code byte or const a nt from progr a m memory. the a ddress of the byte fetched is the s u m of the origin a l u nsigned 8 -bit acc u m u l a tor contents a nd the contents of the u nselected d a t a pointer. the b a se register is not a ltered. s ixteen-bit a ddition is performed so a c a rry-o u t from the low-order eight bits m a y prop a g a te thro u gh higher-order bits. no fl a gs a re a ffected. example: a v a l u e between 0 a nd 3 is in the acc u m u l a tor. the following instr u ctions will tr a nsl a te the v a l u e in the acc u m u l a tor to one of fo u r v a l u es defined by the db (define byte) directive. mov /dptr, #table movc a, @a+pc ret table: db 66h db 77h db 88 h db 99h if the s u bro u tine is c a lled with the acc u m u l a tor eq ua l to 01h, it ret u rns with 77h in the acc u m u l a tor. bytes: 2 cycles: 4 encoding: a5 10010011 operation: movc if (dp s ) = 0 then (a) ( (a) + (dptr1) ) el s e (a) ( (a) + (dptr0) )
181 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22.1.9 mac ab function: m u ltiply a nd acc u m u l a te description: mac ab m u ltiplies the signed 16-bit integers in the register p a irs {ax, a} a nd {bx, b} a nd a dds the 32-bit prod u ct to the 40-bit m register. the low-order bytes of the 16-bit oper a nds a re stored in a a nd b, a nd the high-order bytes in ax a nd bx respectively. the fo u r oper a nd registers a re u n a ffected by the oper a tion. if the a ddition of the prod u ct to the a cc u m u l a ted s u m in m res u lts in a two's complement overflow, the overflow fl a g is set; otherwise it is not cle a red. the c a rry fl a g is set if the res u lt is neg a tive a nd cle a red if positive. example: origin a lly the acc u m u l a tor holds the v a l u e 8 0 (50h). register b holds the v a l u e 160 (0a0h). the instr u ction, mac ab will give the prod u ct 12, 8 00 (3200h), so b is ch a nged to 32h (00110010b) a nd the acc u m u l a tor is cle a red. the overflow fl a g is set, c a rry is cle a red. bytes: 2 cycles: 9 encoding: a5 10100100 operation: mac (m 39-0 ) (m) + { (ax), (a) } x { (bx), (b) } 22.1.10 mov /dptr, #data16 function: lo a d altern a te d a t a pointer with a 16-bit const a nt description: mov /dptr, #d a t a 16 lo a ds the u nselected d a t a pointer with the 16-bit const a nt indic a ted. the third byte is the high-order byte, while the fo u rth byte holds the lower-order byte. no fl a gs a re a ffected. example: when dp s = 0, the instr u ction seq u ence, mov dptr, # 1234h mov /dptr, # 567 8 h lo a ds the v a l u e 1234h into the first d a t a pointer: dph0 holds 12h a nd dpl0 holds 34h; a nd lo a ds the v a l u e 567 8 h into the second d a t a pointer: dph1 hold 56h a nd dpl1 holds 7 8 h. bytes: 2 cycles: 3 encoding: a5 90 immed. d a t a 15- 8 immed. d a t a 7-0 operation: mov if (dp s ) = 0 then (dp1h) #d a t a 15- 8 (dp1l) #d a t a 7-0 el s e (dp0h) #d a t a 15- 8 (dp0l) #d a t a 7-0
182 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 22.1.11 movx a, @/dptr function: move extern a l u sing altern a te d a t a pointer description: the movx instr u ction tr a nsfers d a t a from extern a l d a t a memory to the acc u m u l a tor. the u nselected d a t a pointer gener a tes a 16-bit a ddress which t a rgets edata, fdata or xdata. example: dp s = 0, dptr0 cont a ins 0123h a nd dptr1 cont a ins 4567h. the following instr u ction seq u ence, movx a, @dptr movx @/dptr, a copies the d a t a from a ddress 0123h to 4567h. bytes: 2 cycles: 3 (edata) 5 (fdata or xdata) encoding: a5 11100000 operation: movx if (dp s ) = 0 (a) ((dptr1)) el s e (a) ((dptr0)) 22.1.12 movx @/dptr, a function: move extern a l u sing altern a te d a t a pointer description: the movx instr u ction tr a nsfer d a t a from the acc u m u l a tor to extern a l d a t a memory. the u nselected d a t a pointer gener a tes a 16-bit a ddress which t a rgets edata, fdata or xdata. example: dp s = 0, dptr0 cont a ins 0123h a nd dptr1 cont a ins 4567h. the following instr u ction seq u ence, movx a, @dptr movx @/dptr, a copies the d a t a from a ddress 0123h to 4567h. bytes: 2 cycles: 3 (edata) 5 (fdata or xdata) encoding: a5 11110000 operation: movx if (dp s ) = 0 then ((dptr1)) (a) el s e ((dptr0)) (a)
183 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 23. on-chip debug system the at 8 9lp51rb2/rc2/ic2 on-chip deb u g (ocd) s ystem u ses a two-wire seri a l interf a ce to control progr a m flow; re a d, modify, a nd write the system st a te; a nd progr a m the nonvol a tile memory. the ocd s ystem h a s the following fe a t u res: ? complete progr a m flow control ?re a d-modify-write a ccess to a ll intern a l s frs a nd d a t a memories ?fo u r h a rdw a re progr a m a ddress bre a kpoints ?fo u r progr a m/d a t a a ddress bre a kpoints config u r a ble in 2 m a sk a ble p a irs. ? unlimited progr a m softw a re bre a kpoints u sing break instr u ction ?bre a k on ch a nge in progr a m memory flow ?bre a k on st a ck overflow/ u nderflow ?bre a k on w a tchdog overflow ?bre a k on reset ? non-intr u sive oper a tion ?progr a mming of nonvol a tile memory 23.1 physical interface the on-chip deb u g s ystem u ses a two-wire synchrono u s seri a l interf a ce to est a blish comm u ni- c a tion between the t a rget device a nd the controlling em u l a tor system. the ocd interf a ce is en a bled by cle a ring the ocd en a ble f u se. the ocd device connections a re shown in fig u re 23-1 . when ocd is en a bled, the r s t port pin is config u red a s a n inp u t for the deb u g clock (dcl). p4.3 is a bi-direction a l d a t a line for the deb u g d a t a (dda). when designing a system where on-chip deb u g will be u sed, the following observ a tions m u st be considered for correct oper a tion: ?r s t c a nnot be connected directly to v dd or gnd a nd a ny extern a l c a p a citors or s u pervisors connected to r s t m u st be removed. ? all extern a l reset so u rces m u st be removed. ? ocd is shipped dis a bled from the f a ctory. a device progr a mmer is req u ired to en a ble this f u se before deb u gging c a n occ u r. ?en a bling ocd dis a bles the r s t inp u t a nd thereby dis a bles the in- s ystem progr a mming interf a ce (i s p). i s p c a n only be re-entered by holding r s t a ctive a t power- u p. the bootlo a der rem a ins a ctive a nd h a s priority over the ocd system. figure 23-1. at 8 9lp51rb2/rc2/ic2 on-chip deb u g connections vdd p4.3 r s t gnd dcl dda pol gnd or vdd at 8 9lp51rb2/rc2/ic2
184 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 23.2 software breakpoints the at 8 9lp51rb2/rc2/ic2 microcontroller incl u des a break instr u ction for implementing progr a m memory bre a kpoints in softw a re. a softw a re bre a kpoint c a n be inserted m a n ua lly by pl a cing the break instr u ction in the progr a m code. s ome em u l a tor systems m a y a llow for au to- m a tic insertion/deletion of softw a re bre a kpoints. the fl a sh memory m u st be re-progr a mmed e a ch time a softw a re bre a kpoint is ch a nged. freq u ent insertions/deletions of softw a re bre a k- points will red u ce the end u r a nce of the nonvol a tile memory. devices u sed for deb u gging p u rposes sho u ld not be shipped to end c u stomers. the break instr u ction is tre a ted a s a two- cycle nop when ocd is dis a bled. 23.3 limitations of on-chip debug the at 8 9lp51rb2/rc2/ic2 is a f u lly-fe a t u red microcontroller th a t m u ltiplexes sever a l f u nctions on its limited i/o pins. s ome device f u nction a lity m u st be s a crificed to provide reso u rces for on- chip deb u gging. the on-chip deb u g s ystem h a s the following limit a tions: ?the deb u g clock pin (dcl) is physic a lly loc a ted on the s a me pin a s the extern a l reset (r s t). therefore, a n extern a l reset so u rce is u n a v a il a ble a nd m u st be em u l a ted when ocd is en a bled. the reset o u tp u t fe a t u re is a lso dis a bled except d u ring por ?the deb u g d a t a pin dda is physic a lly loc a ted on the s a me pin a s p4.3. the p4.3 i/o f u nction c a nnot be em u l a ted in this mode ? the bootlo a der h a s priority over ocd. deb u gging is not possible when the bootlo a der is a ctive (bljb = 0 or h a rdw a re entry triggered) ?progr a mming of a ny h a rdw a re lockbit will dis a ble ocd ? the ocd pins a re not bonded in the 40-pin pdip p a ck a ge. in order to deb u g the device, one of the 44-pin p a ck a ges m u st be u sed
185 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24. flash memory programming the atmel at 8 9lp51rb2/rc2/ic2 microcontroller fe a t u res 24k/32k bytes of on-chip in- s ystem progr a mm a ble fl a sh progr a m memory. in- s ystem progr a mming a llows progr a mming a nd reprogr a mming of the microcontroller positi oned inside the end system. the progr a mmer com- m u nic a tes seri a lly with the at 8 9lp51rb2/rc2/ic2 microcontroller, reprogr a mming a ll nonvol a tile memories on the chip. in- s ystem progr a mming elimin a tes the need for physic a l remov a l of the chips from the system. this will s a ve time a nd money, both d u ring development in the l a b, a nd when u pd a ting the softw a re or p a r a meters in the field. the at 8 9lp51rb2/rc2/ic2 provides the following progr a mming interf a ces: ? high-speed, four-wire spi-based programming interface (isp) this synchrono u s h a rdw a re interf a ce progr a ms the device while it is in reset a nd therefore, does not req u ire the cpu to be oper a tion a l, i.e. no clock is req u ired except the s pi seri a l clock. this interf a ce c a n be u sed both in-system a nd in a st a nd- a lone progr a mmer, a nd h a s f u ll a ccess to a ll nonvol a tile memory reso u rces. this interf a ce is comp a tible with the atmel at 8 9lp i s p s t u dio softw a re. s ee s ection 24.6 ?in- s ystem progr a mming (i s p)? on p a ge 214 for more inform a tion. ? 12-pin parallel programming interface (prl) this interf a ce is a s u bmode of the s pi interf a ce th a t a llows d a t a to be re a d/written one 8 -bit byte a t a time inste a d of seri a lly 1-bit a t a time. this interf a ce is intended only for st a nd- a lone progr a mmers. an 8 7c51-comp a tible p a r a llel interf a ce is not a v a il a ble. s ee s ection 24.6.1 ?physic a l interf a ce? on p a ge 214 for more inform a tion. ? rom-based uart serial bootloader (boot) when u sing this 2-pin a synchrono u s interf a ce, the device r u ns a def au lt softw a re bootlo a der from a n on-chip rom. the system clock m u st be oper a tion a l a nd will limit the speed a t which the interf a ce f u nctions. this interf a ce is intended for in-system u se. it h a s f u ll a ccess to the fl a sh code memory, b u t does not h a ve a ccess to a ll config u r a tion options. this interf a ce is comp a tible with the atmel flip softw a re. s ee s ection 24.5 ?bootlo a der? on p a ge 199 for more inform a tion. ? user-defined bootloader and/or in-application programming (iap) the rom bootlo a der c a n c a ll a u ser-defined bootlo a der loc a ted within the code memory inste a d of the def au lt uart bootlo a der. the u ser is free to u se a ny a v a il a ble interf a ce to progr a m the device. the rom a lso cont a ins a n a pplic a tion progr a mming interf a ce (api) th a t implements the low-level ro u tines necess a ry to perform in- a pplic a tion progr a mming (iap). it is recommended th a t u sers employ these f u nctions inste a d of writing their own low-level ro u tines. adv a nced u sers m a y wish to implement their own ro u tines in some c a ses. s ee s ection 24.4 ?in-applic a tion progr a mming (iap)? on p a ge 190 . none of the progr a mming interf a ces req u ire a n extern a l dedic a ted progr a mming volt a ge. the necess a ry high progr a mming volt a ge is gener a ted on-chip u sing the st a nd a rd v dd pin of the microcontroller. note: in this doc u ment the term bootloader , or boot , is u sed to when referring to the uart-b a sed rom bootlo a der a nd in-system programming , or isp, is u sed with reference to the s pi-b a sed interf a ce. this is different from at 8 9c51rb2/rc2/ic2 where i s p a lso referred to the bootlo a der ( a s no s pi progr a mming interf a ce w a s present). however, it sho u ld be noted th a t both interf a ces a re perfectly c a p a ble of performing in-system progr a mming, i.e progr a mming the device when it is a lre a dy mo u nted in the fin a l end- u ser system.
186 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.1 memory organization the at 8 9lp51rb2/rc2/ic2 offers 24k/32k bytes of in- s ystem progr a mm a ble nonvol a tile fl a sh code memory. in a ddition, the device cont a ins a 512-byte user s ign a t u re arr a y, a 12 8 -byte re a d-only atmel s ign a t u re arr a y a nd 19 user config u r a tion f u ses. the memory org a - niz a tion is shown in t a ble 24-1 a nd fig u re 24-1 . the code memory a nd au xili a ry memories a re divided into p a ges of 12 8 bytes e a ch a nd sh a re a tempor a ry p a ge b u ffer of 64 bytes (one h a lf p a ge). a single p a ge er a se oper a tion will er a se a n entire 12 8 -byte p a ge, while a single write oper a tion will only progr a m h a lf of a p a ge. therefore, two write oper a tions a re req u ired for every er a se oper a tion when the whole p a ge m u st be reprogr a mmed. this det a il is tr a nsp a rent to the u ser when u sing the bootlo a der or fl a sh api. figure 24-1. at 8 9lp51rb2/rc2/ic2 memory org a niz a tion . 24.1.1 user signature array the at 8 9lp51rb2/rc2/ic2 incl u des a 512-byte user s ign a t u re arr a y in fo u r 12 8 -byte p a ges. the user s ign a t u re arr a y is a v a il a ble for seri a l n u mbers, firmw a re revision inform a tion, d a te table 24-1. at 8 9lp51rb2/rc2/ic2 memory org a niz a tion memory capacity page size # pages address range code fl a sh 3276 8 bytes 12 8 bytes 256 0000h ? 7fffh user s ign a t u re 512 bytes 12 8 bytes 4 0000h ? 01ffh atmel s ign a t u re 12 8 bytes 12 8 bytes 1 0200h ? 027fh page 511 low page 510 low u s er fu s e row u s er signature array atmel signature array code memory 00 3 f 0000 ffff page 0 0000 0fff data memory page 511 high page 510 high 40 7f page 128 page 0 low page 0 low page 1 low page 0 high page 1 high page 0 low page 1 low page 0 low page 1 high page 1 high page 0 high 00 3 f page buffer 00 1f page 2 low page 3 low page 2 high page 3 high ssb bsb sbv osccal 00 3 f40 7f 00 1f page buffer
187 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary codes or other u ser p a r a meters. the user s ign a t u re arr a y m a y only be written by a n extern a l i s p progr a mmer when the user s ign a t u re progr a mming f u se is en a bled. when the f u se is en a bled, chip er a se will a lso er a se the third p a ge of the a rr a y. when the f u se is dis a bled, none of the p a ges a re a ffected by p a ge er a se/write comm a nds a nd only p a ges one a nd two will be er a sed by chip er a se. t a ble 24-3 s u mm a rizes this beh a vior. progr a mming of the s ign a t u re arr a y is a lso dis a bled by the lock bits. however, re a ding the sign a t u re is a lw a ys a llowed a nd the a rr a y sho u ld not be u sed to store sec u rity sensitive inform a tion. the user s ign a t u re arr a y m a y be modified d u ring exec u tion thro u gh the in-applic a tion progr a mming interf a ce, reg a rdless of the st a te of the user s ign a t u re progr a mming f u se or lock bits. s ome loc a tions of the user s ign a t u re arr a y h a ve speci a l me a ning for the system a s shown in t a ble 24-2 . p a ges one a nd two store bytes necess a ry for bootlo a der oper a tion ( s ee ?boot- lo a der? on p a ge 199 ). p a ge three stores a c a libr a tion byte for the intern a l rc oscill a tor. this byte is re a d a t power- u p to set the freq u ency of the oscill a tor. other bytes in these p a ges m a y be u sed a s a ddition a l sign a t u re sp a ce; however, c a re sho u ld be t a ken to preserve the p a r a me- ter v a l u es when modifying other bytes in the s a me p a ge. note: 1. the oscill a tor c a libr a tion byte controls the freq u ency of the intern a l rc oscill a tor. the fre- q u ency is inversely proportion a l to the c a libr a tion v a l u e s u ch th a t higher v a l u es res u lt in lower freq u encies. a copy of the f a ctory-set c a libr a tion v a l u e is stored a t loc a tion 000 8 h of the atmel s ign a t u re. notes: 1. d u ring i s p, a p a ge er a se/write of the u ser sign a t u re is only a llowed when the user s ign a t u re progr a mming f u se is a ctive. 2. chip er a se will er a se this p a ge only if the user s ign a t u re progr a mming f u se is a ctive. table 24-2. user s ign a t u re p a r a meter bytes name definition location default value b s bboot s t a t u s byte 0000h ffh s bv s oftw a re boot vector 0001h fch (or ffh) ss b s oftw a re s ec u rity byte 00 8 0h ffh o s ccal oscill a tor c a libr a tion 01 8 0h (1) table 24-3. user s ign a t u re i s p progr a mming beh a vior page # address chip erase page erase page write 0 0000?007fh ye s by f u se (1) by f u se (1) 100 8 0?00hfh ye s by f u se (1) by f u se (1) 2 0100?017fh by f u se (2) by f u se (1) by f u se (1) 301 8 0?01ffh no by f u se (1) by f u se (1)
188 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.1.2 atmel signature array the atmel s ign a t u re arr a y is a 12 8 -byte re a d-only a rr a y th a t cont a ins the device id a nd rel a ted inform a tion. the device id v a l u es a re shown in t a ble 24-4 . a copy of the o s ccal c a libr a tion byte is a lso stored a t a ddress 000 8 h. 24.2 user configuration fuses the at 8 9lp51rb2/rc2/ic2 incl u des 19 u ser f u ses for config u r a tion of the device. e a ch f u se is a ccessed a t a sep a r a te a ddress in the user f u se row, with e a ch byte representing one f u se a s listed in t a ble 24-5 . from a progr a mming st a ndpoint, f u ses a re tre a ted the s a me a s norm a l code bytes except they a re not a ffected by chip er a se. f u ses c a n be cle a red a t a ny time by writ- ing 00h to the a ppropri a te loc a tions in the f u se row. however, to set a f u se, i.e. write it to ffh the entire f u se row m u st be er a sed a nd then reprogr a mmed. the progr a mmer sho u ld re a d the st a te of a ll the f u ses into a tempor a ry loc a tion, modify those f u ses which need to be dis a bled, then iss u e a f u se write with a u to-er a se comm a nd u sing the tempor a ry d a t a . note th a t the bootlo a der only h a s limited a ccess to the f u ses. for f u ll device config u r a tion a n extern a l i s p progr a mmer is req u ired. table 24-4. device id v a l u es in atmel s ign a t u re device 00h 01h 02h 30h 31h 60h 61h at 8 9lp51rb2 1eh 62h 72h 5 8 hd7hechefh at 8 9lp51rc2 1eh 63h 72h 5 8 hd7hechefh at 8 9lp51ic2 1eh 63h 69h 5 8 hd7hechefh table 24-5. user config u r a tion f u se definitions address fuse name description 00 ? 01h clock s o u rce a ? c s a[0:1] (2) s elects so u rce for the system clock when u sing o s ca: c s a1 c s a0 s elected s o u rce ffh ffh high s peed cryst a l oscill a tor on xtal1a/xtal2a (xtal) ffh 00h low power cryst a l oscill a tor on xtal1a/xtal2a (xtal) 00h ffh extern a l clock on xtal1a (xclk) 00h 00h intern a l 8 mhz rc oscill a tor (irc) 02 ? 03h s t a rt- u p time ? s ut[0:1] s elects time-o u t del a y for the por/bod/pwd w a ke- u p period: s ut1 s ut0 s elected time-o u t 00h 00h 1 ms (xtal); 16 s (xclk/irc) 00h ffh 2 ms (xtal); 512 s (xclk/irc) ffh 00h 4 ms (xtal); 1 ms (xclk/irc) ffh ffh 16 ms (xtal); 4 ms (xclk/irc) 04h bootlo a der j u mp bit ffh: reset to u ser a pplic a tion a t 0000h 00h: reset to rom bootlo a der a t f 8 00h 05h extern a l ram en a ble ffh: extern a l ram en a bled a t reset (extram = 1) 00h: extern a l ram dis a bled a t reset (extram = 0) 06h comp a tibility mode ffh: cpu f u nctions in 12-clock comp a tibility mode 00h: cpu f u nctions is si ngle-cycle f a st mode 07h i s p en a ble (3) ffh: in- s ystem progr a mming en a bled 00h: in- s ystem progr a mming dis a bled (en a bled a t por only)
189 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. the def au lt st a te from the f a ctory for a ll f u ses is ffh, except for the bootlo a der j u mp bit, which is 00h. 2. ch a nges to these f u ses will only t a ke effect a fter a device por. 3. ch a nges to these f u ses will only t a ke effect a fter the i s p session termin a tes by bringing r s t in a ctive. 24.3 flash hardware security the at 8 9lp51rb2/rc2/ic2 provides three h a rdw a re s ec u rity bits (or lock bits) for fl a sh code memory sec u rity. s ec u rity bits c a n be left u nprogr a mmed (ffh) or progr a mmed (00h) to obt a in the protection levels listed in t a ble 24-6 . s ec u rity bits c a n only be er a sed (set to ffh) by chip er a se. lock bit mode 2 dis a bles progr a mming of a ll memory sp a ces, incl u ding the user s ign a t u re arr a y a nd user config u r a tion f u ses. user f u ses m u st be progr a mmed before en a bling lock bit mode 2 or 3. lock bit mode 3 implements mode 2 a nd a lso blocks re a ds from the code a nd d a t a memories; however, re a ds of the user s ign a t u re arr a y, atmel s ign a t u re arr a y, a nd user config u r a tion f u ses a re still a llowed. the h a rdw a re s ec u rity bits only restrict the a ccess of the s pi-b a sed i s p interf a ce. the h a rd- w a re s ec u rity bits will not dis a ble the bootlo a der or a ny progr a mming initi a ted by the a pplic a tion softw a re u sing iap. 0 8 h x1/x2 mode ffh: x1 mode ( s ystem clock is divided-by-two) 00h: x2 mode ( s ystem clock is not divided-by-two) 09h ocd en a ble ffh: on-chip deb u g is dis a bled 00h: on-chip deb u g is en a bled 0ah user s ign a t u re progr a mming ffh: progr a mming of user s ign a t u re dis a bled 00h: progr a mming of user s ign a t u re en a bled 0bh trist a te ports ffh: i/o ports st a rt in inp u t-only mode (trist a ted) a fter reset 00h: i/o ports st a rt in q ua si-bidirection a l mode a fter reset 0ch reserved 0d ? 0eh low power mode ? lpm[0:1] s elects so u rce for the system clock when u sing o s ca: lpm1 lpm0 power mode ffh ffh low power mode ffh 00h norm a l mode 00h ffh extr a low power mode (f o s c 1 mhz) 00h 00h norm a l mode 0fh r1 en a ble ffh: 5 m resistor on xtal1a dis a bled 00h: 5 m resistor on xtal1a en a bled 10h oscill a tor s elect 00h: boot from oscill a tor b (at 8 9lp51ic2 only) ffh: boot from oscill a tor a 11 ? 12h clock s o u rce b ? c s b[0:1] (2) s elects so u rce for the system clock when u sing o s cb (at 8 9lp51ic2 only): c s b1 c s b0 s elected s o u rce ffh ffh low freq u ency cryst a l oscill a tor on xtal1b/xtal2b (xtal) ffh 00h low freq u ency cryst a l oscill a tor on xtal1b/xtal2b (xtal) 00h ffh extern a l clock on xtal1b (xclk) 00h 00h intern a l 8 mhz rc oscill a tor (irc) table 24-5. user config u r a tion f u se definitions address fuse name description
190 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.4 in-application programming (iap) the at 8 9lp51rb2/rc2/ic2 s u pports in-applic a tion progr a mming (iap), a llowing the progr a m memory to be modified d u ring exec u tion. iap c a n be u sed to modify the u ser a pplic a tion on the fly or to u se progr a m memory for nonvol a tile d a t a stor a ge. the at 8 9lp51rb2/rc2/ic2 incl u des a fl a sh applic a tion progr a mming interf a ce (api) a s p a rt of the bootlo a der rom code. the fl a sh api is the preferred w a y to progr a m the fl a sh memory from the a pplic a tion code. adv a nced u sers looking to write their own low-level ro u tines sho u ld refer to s ection 24.4.2 on p a ge 192 . 24.4.1 api call description the in-applic a tion progr a mming (iap) fe a t u re a llows reprogr a mming a microcontroller on-chip fl a sh memory witho u t removing it from the system a nd while the embedded a pplic a tion is r u n- ning. the u ser a pplic a tion c a n c a ll fl a sh applic a tion progr a mming interf a ce (api) ro u tines a llowing iap. these fl a sh api a re a lso exec u ted by the bootlo a der. to c a ll the corresponding api, the u ser m a y u se a set of ro u tines which c a n be linked with the a pplic a tion. ex a mple of fl a sh_ a pi ro u tines a re a v a il a ble on the atmel web site on the softw a re a pplic a tion note: c fl a sh drivers for the at 8 9c51rd2/ed2 the api c a lls description a nd a rg u ments a re shown in t a ble 24-7 . the a pplic a tion selects a n api by setting r1, acc, dptr0 a nd dptr1 registers. all c a lls a re m a de thro u gh a common interf a ce ?u s er_call? a t the a ddress fff0h. the j u mp to the u s er_call m u st be done by a n lcall instr u ction in order to be a ble to ret u rn to the a pplic a - tion. before j u mping to u s er_call, the bit enboot in auxr1 register m u st be set to m a p the rom code into the a ddress sp a ce. fl a sh api c a lls h a ve the following constr a ints: ? the interr u pts a re not dis a bled by the bootlo a der. interr u pts m u st be dis a bled by the u ser prior to c a lling u s er_call, then re-en a bled when ret u rning. ?the u ser m u st feed the h a rdw a re w a tchdog before l au nching a fl a sh oper a tion. ? the api c a ll req u ires a minim u m of two free st a ck bytes table 24-6. s ec u rity protection modes program lock bits (by address) mode 00h 01h 02h protection mode 1 ffh ffh ffh no progr a m lock fe a t u res 200hffhffhf u rther progr a mming of the fl a sh is dis a bled 300h00hffhf u rther progr a mming of the fl a sh is dis a bled a nd verify (re a d) is a lso dis a bled 4 00h 00h 00h f u rther progr a mming of the fl a sh is dis a bled a nd verify (re a d) is a lso dis a bled; extern a l exec u tion a bove 32k when bm s =1 is dis a bled
191 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 24-7. api c a ll su mm a ry command r1 a dptr0 dptr1 returned value command effect read manuf id 00h xxh 0000h xxh acc = m a n u f a ct u rer id re a d m a n u f a ct u rer identifier read device id1 00h xxh 0001h xxh acc = device id 1 re a d device identifier 1 read device id2 00h xxh 0002h xxh acc = device id 2 re a d device identifier 2 read device id3 00h xxh 0003h xxh acc = device id 3 re a d device identifier 3 era s e block 01h xxh dph = 00h 00h acc = dph er a se block 0 dph = 20h er a se block 1 dph = 40h er a se block 2 dph = 8 0h er a se block 3 dph = c0h er a se block 4 program data byte 02h v a l u e to write address of byte to progr a m xxh acc = 0: done progr a m u p one d a t a byte in the on-chip fl a sh memory. program ss b 05h xxh 0000h 00h acc = ss b v a l u e s et ss b level 1 0001h s et ss b level 2 0010h s et ss b level 0 0011h s et ss b level 1 program b s b 06h new b s b v a l u e 0000h xxh none progr a m boot st a t u s byte program s bv 06h new s bv v a l u e 0001h xxh none progr a m softw a re boot vector read ss b 07h xxh 0000h xxh acc = ss bre a d s oftw a re s ec u rity byte read b s b 07h xxh 0001h xxh acc = b s bre a d boot s t a t u s byte read s bv 07h xxh 0002h xxh acc = s bv re a d s oftw a re boot vector program data pag e 09h n u mber of byte to progr a m address of the first byte to progr a m in the fl a sh memory address in xram of the first d a t a to progr a m acc = 0: done progr a m u p to 12 8 bytes in u ser fl a sh. rem a rk: n u mber of bytes to progr a m is limited s u ch a s the fl a sh write rem a ins in a single 12 8 bytes p a ge. hence, when acc is 12 8 , v a lid v a l u es of dpl a re 00h, or, 8 0h. program x2 fu s e0ah f u se v a l u e 00h or 01h 000 8 h xxh none progr a m x2 f u se bit with acc program bljb fu s e 0ah f u se v a l u e 00h or 01h 0004h xxh none progr a m bljb f u se bit with acc read h s b 0bh xxh xxxxh xxh acc = h s bre a d h a rdw a re byte read boot id1 0eh xxh dpl = 00h xxh acc = id1 re a d boot id1 read boot id2 0eh xxh dpl = 01h xxh acc = id2 re a d boot id2 read boot ver s ion 0fh xxh xxxxh xxh acc = boot_version re a d bootlo a der version
192 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.4.2 low-level interface the cpu interf a ces to the fl a sh memory thro u gh the fcon register ( t a ble 24-10 ) a nd eecon register ( t a ble 24-11 on p a ge 19 8 ). these registers a re u sed to: ?m a p the memory sp a ces in the a ddress a ble sp a ce ?l au nch the progr a mming of the memory sp a ces ? get the st a t u s of the fl a sh memory (b u sy/not b u sy) caution : the incorrect u s a ge of these f u nctions c a n m a ke the system u nst a ble or inoper a ble. for intern a l exec u tion from u ser sp a ce the at 8 9lp51rb2/rc2/ic2 u ses a n idle-while-write a rchitect u re where the cpu is pl a ced in a n idle st a te while progr a mming occ u rs. when the write completes, the cpu will contin u e exec u ting with the instr u ction a fter the instr u ction th a t st a rted the write seq u ence ( u s ua lly a mov to fcon). all peripher a ls will contin u e to f u nction d u ring the write cycle; however, interr u pts will not be serviced u ntil the write completes. for extern a l exec u tion from u ser sp a ce the at 8 9lp51rb2/rc2/ic2 u ses a n execute-while- write a rchitect u re where the cpu contin u es to oper a te while the progr a mming occ u rs. the soft- w a re sho u ld poll the st a te of the fbu s y fl a g to determine when the write completes. interr u pts m u st be dis a bled d u ring the write seq u ence a s the cpu will not be a ble to vector to the intern a l interr u pt t a ble a nd c a re sho u ld be t a ken th a t the a pplic a tion does not j u mp to a n intern a l a ddress u ntil the progr a mming completes. the fl a sh api ro u tines in the boot rom a lso u se e xecute-while-write. interr u pts m u st be dis- a bled before c a lling the ro u tines to prevent the cpu from vectoring to a non-rom a ddress before the progr a mming completes. fl a sh memory u ses a p a ge-b a sed progr a mming model. fl a sh d a t a memory differs from tr a di- tion a l eeprom d a t a memory in the method of writing d a t a . eeprom gener a lly c a n u pd a te a single byte with a ny v a l u e. fl a sh memory splits progr a mming into write a nd er a se oper a tions. a fl a sh write c a n only progr a m zeroes, i.e ch a nge ones into zeroes ( ). any ones in the write d a t a a re ignored. a fl a sh er a se sets a n entire p a ge of d a t a to ones so th a t a ll bytes become ffh. therefore a fter a n er a se, e a ch byte in the p a ge c a n only be written once with a ny possible v a l u e. bytes c a n be overwritten witho u t a n er a se a s long a s only ones a re ch a nged into zeroes. however, if even a single bit needs u pd a ting from zero to one ( ); then the contents of the p a ge m u st first be s a ved, the entire p a ge m u st be er a sed a nd the zero bits in a ll bytes (old a nd new d a t a combined) m u st be written. avoiding u nnecess a ry p a ge er a ses gre a tly improves the end u r a nce of the memory. 24.4.2.1 mapping of the memory space by def au lt, the u ser a pplic a tion sp a ce of the fl a sh code memory is a ccessed re a d-only by the movc instr u ction. the fl a sh tempor a ry p a ge b u ffer is m a de a ccessible (write-only) by setting the fp s bit in fcon register. writing is possible from 0000h to fffff, a ddress bits 6 to 0 a re u sed to select a n a ddress within a p a ge while bits 15 to 7 a re u sed to select the progr a mming a ddress of the p a ge. s etting fp s t a kes precedence over the extram bit in auxr. the other memory sp a ces (user a nd atmel s ign a t u res, user f u ses, h a rdw a re s ec u rity) a re m a de a ccessible in the code segment by progr a mming bits fmod0 a nd fmod1 in fcon regis- ter in a ccord a nce with t a ble 24- 8 . a movc instr u ction c a n then be u sed for re a ding these sp a ces. 10
193 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.4.2.2 launching programming the fpl bits in the fcon register a re u sed to sec u re the l au nch of progr a mming. a specific seq u ence m u st be written in these bits to u nlock the write protection a nd to l au nch the progr a m- ming. this seq u ence is 5xh followed by axh. t a ble 24-9 s u mm a rizes the progr a mming of the memory sp a ces a ccording to the fmod bits. notes: 1. the seq u ence 5xh a nd axh m u st be exec u ting witho u t instr u ctions between them otherwise the progr a mming is a borted. 2. interr u pts th a t m a y occ u r d u ring progr a mming time m u st be dis a bled to a void a ny sp u rio u s exit of the progr a mming mode. 24.4.2.3 status of the flash memory the bit fbu s y in fcon register is u sed to indic a te the st a t u s of progr a mming. fbu s y is set when progr a mming is in progress a nd cle a red when the progr a mming completes. if progr a m- ming w a s interr u pted d u e to a brown-o u t condition the err fl a g in eecon is set. 24.4.2.4 loading the page buffer the at 8 9lp51rb2/rc2/ic2 incl u des a tempor a ry p a ge b u ffer of 64 bytes, or one h a lf of a p a ge. bec au se the p a ge b u ffer is 64 bytes long, the m a xim u m n u mber of bytes written a t one time is 64. therefore, two write cycles a re req u ired to fill a n entire 12 8 -byte p a ge, one for the low h a lf p a ge (00h?3fh) a nd one for the high h a lf p a ge (40h?7fh) a s shown in fig u re 24-2 . table 24-8. memory s election fmod1 fmod0 addressable space 0 0 user applic a tion (0000?ffffh) 01 user s ign a t u re (0000?01ffh) atmel s ign a t u re (0200?027fh re a d-only) 10 user f u ses (0000?007fh) h a rdw a re s ec u rity bits (00 8 0?00ffh re a d-only) 11reserved table 24-9. progr a mming s eq u ences memory write to fcon operation fpl 3-0 fps fmod1 fmod0 user applic a tion (code) 5x00no a ction ax0 0 write the p a ge b u ffer to u ser sp a ce (0000?ffffh) user s ign a t u re 5x01no a ction ax0 1 write the p a ge b u ffer to user s ign a t u re sp a ce (0000?01ffh) user f u ses 5x10no a ction ax1 0 write the p a ge b u ffer to user f u se sp a ce (0000?007fh) reserved 5x11no a ction ax1 1no a ction
194 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-2. p a ge progr a mming s tr u ct u re any n u mber of d a t a bytes from 1 to 64 c a n be lo a ded into the tempor a ry p a ge b u ffer. this pro- vides the c a p a bility to progr a m the whole memory by byte, by h a lf-p a ge or by a ny n u mber of bytes in a h a lf-p a ge. note th a t once lo a ded, a b u ffer loc a tion c a nnot be relo a ded with a nother v a l u e. the p a ge b u ffer is au tom a tic a lly cle a red a fter e a ch er a se/write oper a tion. by def au lt no er a se is performed prio r to writing the p a ge b u ffer contents to the fl a sh a rr a y. any u nlo a ded loc a tions rem a in u nch a nged. any zeroes in the lo a ded loc a tions will be written to the desired p a ge. the au to-er a se bit aer s (eecon.6) c a n be set to one to perform a p a ge er a se au tom a tic a lly a t the beginning of a ny write seq u ence. the p a ge er a se will er a se the entire p a ge, i.e. both the low a nd high h a lf p a ges. however, the write oper a tion p a ired with the au to-er a se c a n only progr a m one of the h a lf p a ges. a second write cycle witho u t au to-er a se is req u ired to u pd a te the other h a lf p a ge. when aer s =1 a ny u nlo a ded loc a tions will be left bl a nk (ffh) a fter the oper a tion completes. the following proced u re is u sed to lo a d the p a ge b u ffer a nd is s u mm a rized in fig u re 24-3 : 1. sa ve then dis a ble interr u pts (ea = 0) 2. m a p the p a ge b u ffer sp a ce by setting fp s =1 3. lo a d the dptr (or /dptr) with the a ddress to lo a d 4. lo a d acc u m u l a tor register with the d a t a to lo a d 5. exec u te the movx @dptr, a instr u ction (or movx @/dptr, a instr u ction) 6. if needed loop the steps 3?5 u ntil the p a ge b u ffer is completely lo a ded 7. unm a p the p a ge b u ffer (fp s =0) a nd restore interr u pts (ea = 1) 24.4.2.5 programming the flash code space the following proced u re is u sed to progr a m the user code sp a ce a nd is s u mm a rized in fig u re 24-4 : 1. lo a d u p to one h a lf-p a ge of d a t a in the p a ge b u ffer from a ddress 0000h to ffffh 2. sa ve then dis a ble the interr u pts (ea = 0) 3. l au nch the progr a mming by writing the d a t a seq u ence 50h followed by a0h to fcon register 4. if l au nched from intern a l memory, the cpu idles u ntil progr a mming completes. if l au nched from extern a l memory, poll the fbu s y fl a g u ntil it is cle a red 5. restore the interr u pts (ea = 1) low half page 00 3 f data memory high half page 40 7f 00 3 f page buffer
195 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-3. fl a sh p a ge b u ffer lo a ding proced u re note: the l a st p a ge a ddress u sed when lo a ding the p a ge b u ffer is the one u sed to select the p a ge pro- gr a mming a ddress. 24.4.2.6 programming the user signature space the following proced u re is u sed to progr a m the user s ign a t u re sp a ce a nd is s u mm a rized in fig- u re 24-4 : 1. lo a d u p to one h a lf-p a ge of d a t a in the p a ge b u ffer from a ddress 0000h to 01ffh 2. sa ve then dis a ble the interr u pts (ea = 0) 3. l au nch the progr a mming by writing the d a t a seq u ence 52h followed by a2h to fcon register. 4. if l au nched from intern a l memory, the cpu idles u ntil progr a mming completes. if l au nched from extern a l memory, poll the fbu s y fl a g u ntil it is cle a red 5. restore the interr u pts (ea = 1) flash page buffer loading data load dptr = address acc = data exec: movx @dptr, a last byte to load? page buffer mapping fcon = 08h (fps=1) data memory mapping fcon = 00h (fps = 0) save and disable it ea = 0 restore it
196 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-4. fl a sh progr a mming proced u re 24.4.2.7 programming the user fuse space the following proced u re is u sed to progr a m the user f u se sp a ce a nd is s u mm a rized in fig u re 24-4 : 1. lo a d u p to one h a lf-p a ge of d a t a in the p a ge b u ffer from a ddress 0000h to 01ffh 2. sa ve then dis a ble the interr u pts (ea = 0) 3. l au nch the progr a mming by writing the d a t a seq u ence 54h followed by a4h to fcon register. 4. if l au nched from intern a l memory, the cpu idles u ntil progr a mming completes. if l au nched from extern a l memory, poll the fbu s y fl a g u ntil it is cle a red 5. restore the interr u pts (ea = 1) 24.4.2.8 reading the flash code space the following proced u re is u sed to re a d the user code sp a ce: 1. m a p the code sp a ce by writing 00h to fcon (the def au lt) 2. re a d one byte in acc u m u l a tor by exec u ting movc a,@a+dptr where a+dptr is the a ddress of the code byte to re a d flash spaces programming save and disable it ea = 0 launch programming fcon = 5xh fcon = axh end programming restore it page buffer loading see figure 24-3 fbusy cleared? clear mode fcon = 00h
197 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.4.2.9 reading the user/atmel signature the following proced u re is u sed to re a d the user or atmel s ign a t u re sp a ce a nd is s u mm a rized in fig u re 24-5 : ?m a p the s ign a t u re sp a ce by writing 02h to fcon register ?re a d one byte in acc u m u l a tor by exec u ting movc a,@a+dptr where a+dptr is 0000? 01ffh for the user s ign a t u re a nd 0200?027fh for the atmel s ign a t u re ? cle a r fcon to u nm a p the s ign a t u re sp a ce 24.4.2.10 reading the user fuses/hardware security bits the following proced u re is u sed to re a d the user f u ses or h a rdw a re s ec u rity sp a ce a nd is s u mm a rized in fig u re 24-5 : ?m a p the user f u ses/h a rdw a re s ec u rity sp a ce by writing 04h in fcon register ?re a d one byte in acc u m u l a tor by exec u ting movc a,@a+dptr where a+dptr is 0000? 007fh for the user f u ses a nd 00 8 0?00ffh for the h a rdw a re s ec u rity ? cle a r fcon to u nm a p the user f u ses/h a rdw a re s ec u rity figure 24-5. re a ding proced u re note: aa = 00b for the user applic a tion code aa = 01b for the user/atmel s ign a t u re aa = 10b for the user f u ses/h a rdw a re s ec u rity flash spaces reading flash spaces mapping fcon = 00000aa0 data read dptr = address acc = 0 exec: movc a, @a+dptr clear mode fcon = 00h
198 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 24-10. fcon ? fl a sh control register fcon address = 0d1h reset v a l u e = xxxx 000xb not bit address a ble fpl3 fpl2 fpl1 fpl0 fp s fmod1 fmod0 fbu s y bit76543210 symbol function fpl 3-0 programming launch command bits write 5xh followed by axh to l au nch the progr a mming a ccording to fmod 1-0 . fp s flash map program space s et this bit to direct the movx @dptr, a a nd movx @/dptr, a instr u ctions to the fl a sh memory tempor a ry p a ge b u ffer. cle a r to a llow movx to write reg u l a r d a t a memory. fmod 1-0 flash mode mode fmod1 fmod0 memory operation target 0 0 0 code sp a ce (0000?ffffh) 101 user s ign a t u re sp a ce (0000?01ffh) atmel s ign a t u re sp a ce (0200?027fh re a d-only) 210 user f u se sp a ce (0000?007fh) h a rdw a re s ec u rity sp a ce (00 8 0?00ffh re a d-only) 311reserved fbu s y flash busy s et by h a rdw a re when progr a mming is in progress. cle a red by h a rdw a re when progr a mming is done. c a nnot be ch a nged by softw a re. table 24-11. eecon ? eeprom control register eecon = d2h reset v a l u e = 1000 xxxb not bit address a ble fout aer s ldpg flge inhibit err ? ? bit76543210 symbol function fout when flge = 1, fout is set/cle a red by h a rdw a re d u ring re a ds from edata in the r a nge of 07 8 0h?07ffh to show the byte fl a g st a t u s of the l a st loc a tion a ccessed. fout = 1 when flge = 0. aer s a u to-er a se en a ble. s et to perform a n au to-er a se of a fl a sh memory p a ge d u ring the next write seq u ence. cle a r to perform write witho u t er a se. this bit is reserved for the fl a sh api. ldpg lo a d p a ge en a ble. s et to this bit to lo a d m u ltiple bytes to the tempor a ry p a ge b u ffer. byte loc a tions m a y not be lo a ded more th a n once before a write. ldpg m u st be cle a red before writing. flge byte fl a g en a ble. when flge = 1, writes to edata in the r a nge of 07 8 0h?07ffh will set the byte fl a g of the loc a tion a ccessed. re a ds in the r a nge of 07 8 0h?07ffh will ret u rn the byte fl a g st a t u s in fout. when flge = 0 a ll byte fl a gs a re reset to zero. inhibit write inhibit fl a g. cle a red by h a rdw a re when the volt a ge on vdd h a s f a llen below the minim u m progr a mming volt a ge. s et by h a rdw a re when the volt a ge on vdd is a bove the minim u m progr a mming volt a ge ( a fter 2 ms del a y). err error fl a g. s et by h a rdw a re if a n error occ u rred d u ring the l a st progr a mming seq u ence (fl a sh or eeprom) d u e to a browno u t condition (low volt a ge on vdd). m u st be cle a red by softw a re.
199 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5 bootloader the bootlo a der is a rom-b a sed a pplic a tion th a t provides the following fe a t u res: ?fl a sh intern a l progr a m memory ? boot vector a llows u ser provided fl a sh lo a der code to reside a nywhere in the fl a sh memory sp a ce. this config u r a tion provides flexibility to the u ser. ?def au lt lo a der in boot rom a llows progr a mming vi a the seri a l port witho u t the need of a u ser provided lo a der. ?progr a mming a nd er a sing volt a ge with st a nd a rd power s u pply ?re a d/progr a mming/er a se: ? byte-wise re a d witho u t w a it st a te ? byte or p a ge er a se a nd progr a mming (10 ms) ?typic a l progr a mming time (64k bytes) is 22s with on chip seri a l bootlo a der ?progr a mm a ble sec u rity for the code in the fl a sh ? 100k write cycles ?10 ye a rs d a t a retention the bootlo a der m a n a ges comm u nic a tion a ccording to a specific a lly defined protocol to provide the whole a ccess a nd service on fl a sh memory. f u rthermore, a ll a ccesses a nd ro u tines c a n be c a lled from the u ser a pplic a tion. figure 24-6. di a gr a m context description t a ble 24-12 list some a cronyms u sed by the bootlo a der. on fig u re 24-7 , the on-chip bootlo a der processes a re: bootloader flash memory access via specific protocol access from user application table 24-12. bootlo a d definitions mnemonic definition b s b boot s t a t u s byte hw/h s b h a rdw a re byte/h a rdw a re s ec u rity byte s bv s oftw a re boot vector ss b s oftw a re s ec u rity byte
200 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary ? isp communication managemen t the p u rpose of this process is to m a n a ge the comm u nic a tion a nd its protocol between the on-chip bootlo a der a nd a extern a l device. the on-chip rom implements a seri a l protocol (see section ?bootlo a der protocol description? on p a ge 205 ). this process tr a nsl a te seri a l comm u nic a tion fr a me (uart) into fl a sh memory a ccess (re a d, write, er a se, etc.). ? user call management s ever a l applic a tion progr a m interf a ce (api) c a lls a re a v a il a ble for u se by a n a pplic a tion progr a m to permit selective er a sing a nd progr a mming of fl a sh p a ges. all c a lls a re m a de thro u gh a common interf a ce (api c a lls), incl u ded in the rom bootlo a der. the progr a mming f u nctions a re selected by setting u p the microcontroller?s registers before m a king a c a ll to a common entry point (0xfff0). res u lts a re ret u rned in the registers. the p u rpose on this process is to tr a nsl a te the registers v a l u es into intern a l fl a sh memory m a n a gement. s ee ?in- applic a tion progr a mming (iap)? on p a ge 190 ? flash memory management this process m a n a ges low level a ccess to fl a sh memory (performs re a d a nd write a ccess). figure 24-7. bootlo a der f u nction a l description 24.5.1 bootloader process the bootlo a der c a n be a ctiv a ted by two me a ns: h a rdw a re conditions or reg u l a r boot process. isp communication management user application specific protocol communication management flash memory external host with flash memory user call management (api)
201 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary the h a rdw a re condition p s en = 0 d u ring the de a ssertion of r s t (f a lling edge for pol = 1, ris- ing edge for pol = 0) forces the on-chip bootlo a der exec u tion. this a llows a n a pplic a tion to be b u ilt th a t will norm a lly exec u te the end u ser?s code b u t c a n be m a n ua lly forced into def au lt boot- lo a der oper a tion. as p s en is a a n o u tp u t port in norm a l oper a ting mode a fter reset, u ser a pplic a tion sho u ld t a ke c a re to rele a se p s en a fter the v a lid a ting edge of the reset sign a l. the h a rdw a re condition is s a mpled a t the reset edge, a nd th u s c a n be rele a sed a t a ny time when the reset inp u t is in a ctive. to ens u re correct microcontroller st a rt u p, the p s en pin sho u ld not be tied to gro u nd d u ring power-on ( s ee fig u re 24- 8 ). figure 24-8. h a rdw a re condition typic a l seq u ence d u ring power-on (pol = 1) the on-chip bootlo a der boot process is shown fig u re 24-9 on p a ge 203 a nd described in t a ble . 24.5.2 bootloader resources s ever a l on-chip reso u rces a re provided for u se by the bootlo a der. 24.5.2.1 hardware register the h a rdw a re register of the at 8 9lp51rb2/rc2/ic2 is c a lled the h a rdw a re byte or h a rdw a re s ec u rity byte (h s b). it is a sh a dow of selected reso u rces from the user f u ses a nd h a rdw a re s ec u rity bits. table 24-13. h a rdw a re s ec u rity byte (h s b) bootlo a der process description purpose h a rdw a re condition the h a rdw a re condition forces the bootlo a der exec u tion wh a tever the bljb, b s b a nd s bv v a l u es. bljb the boot lo a der j u mp bit forces the a pplic a tion exec u tion. bljb = 0 => bootlo a der exec u tion bljb = 1 => applic a tion exec u tion the bljb is a user config u r a tion f u se. it c a n be modified by h a rdw a re (progr a mmer) or by softw a re (api). note: the bljb test is performed by h a rdw a re to prevent a ny progr a m exec u tion. s bv the s oftw a re boot vector cont a ins the high a ddress of c u stomer bootlo a der stored in the a pplic a tion. s bv = fch (def au lt v a l u e) if no c u stomer bootlo a der in u ser fl a sh. note: the c u stomer bootlo a der is c a lled by jmp [ s bv]00h instr u ction. vcc psen rst 76543210 x2 bljb - - xram lb2 lb1 lb0
202 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary bit number bit mnemonic description 7x2 x2 mode progr a mmed (?0? v a l u e) to force x2 mode a fter reset. unprogr a mmed (?1? v a l u e) to force x1 mode a fter reset (def au lt). 6bljb boot loader jump bit unprogr a mmed (?1? v a l u e) to st a rt the u ser?s a pplic a tion on next reset a t a ddress 0000h. progr a mmed (?0? v a l u e) to st a rt the boot lo a der a t a ddress f 8 00h on next reset (def au lt). 5o s c oscillator bit progr a mmed to a llow oscill a tor b a t st a rt u p unprogr a mmed this bit to a llow oscill a tor a a t st a rt u p (def au lt). 4- reserved 3xram xram config bit (only programmable by programmer tools) progr a mmed to inhibit xram. unprogr a mmed, this bit to v a lid xram (def au lt). 2-0 lb2-0 user memory lock bits (only programmable by programmer tools) s ee t a ble 24-14
203 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-9. bootlo a der process reset hardware condition? bljb!= 0 ? user application hardware software atmel boot loader user boot loader bljb = 1 bsb = 00h ? sbv = fch ? pc = 0000h pc= [sbv]00h bljb = 0 if bljb = 0 then enboot bit (auxr1) is set else enboot bit (auxr1) is cleared enboot = 1 enboot = 0 yes (p s en = 0, ea = 1, a nd ale =1 or not connected)
204 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.2.2 flash memory lock bits the three lock bits provide different levels of protection for the on-chip code a nd d a t a when pro- gr a mmed a s shown in t a ble 24-14 . these bits in the h s b a re copies of the h a rdw a re s ec u rity bits ( s ee s ection 24.3 on p a ge 1 8 9 ). table 24-14. progr a m lock bits note: u: unprogr a mmed or "one" level. p: progr a mmed or "zero" level. x: do not c a re warning: s ec u rity level 2 a nd 3 sho u ld only be progr a mmed a fter fl a sh a nd code verific a tion. 24.5.2.3 software registers s ever a l registers a re u sed in by the bootlo a der for the boot process. these registers a re in the user s ign a t u re p a rt of the fl a sh memory. they a re a ccessed in the following w a ys: ?comm a nds iss u ed by the i s p progr a mmer ?comm a nds iss u ed by the bootlo a der softw a re. ? api c a lls iss u ed by the a pplic a tion softw a re. s ever a l softw a re registers a re described in t a ble 24-15 . after progr a mming the p a rt by the bootlo a der, the b s b m u st be cle a red (00h) in order to a llow the a pplic a tion to boot a t 0000h. the content of the s oftw a re s ec u rity byte ( ss b) is described in t a ble 24-16 a nd t a ble 24-17 . the ss b protects the fl a sh memory from progr a mming by the bootlo a der the s a me w a y the h a rdw a re s ec u rity bits protect from i s p. program lock bits protection description security level lb0 lb1 lb2 1 u u u no progr a m lock fe a t u res en a bled. 2puu movc instr u ction exec u ted from extern a l progr a m memory is dis a bled from fetching code bytes from intern a l memory, ea is s a mpled a nd l a tched on reset, a nd f u rther p a r a llel progr a mming of the on chip code memory is dis a bled. i s p a nd softw a re progr a mming with api a re still a llowed. 3xpu sa me a s 2, a lso verify code memory thro u gh p a r a llel progr a mming interf a ce is dis a bled. 4xxp sa me a s 3, a lso extern a l exec u tion is dis a bled (def au lt). table 24-15. bootlo a der s oftw a re registers mnemonic definition default value s bv s oftw a re boot vector fch b s b boot s t a t u s byte ffh ss b s oftw a re s ec u rity byte ffh
205 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table 24-16. s oftw a re s ec u rity byte the two lock bits provide different leve ls of protection for the on-chip code a nd d a t a , when pro- gr a mmed a s shown in t a ble 24-17 . table 24-17. user memory lock bits of the ss b note: x: do not c a re warning: s ec u rity level 2 a nd 3 sho u ld only be progr a mmed a fter fl a sh verific a tion. 24.5.3 bootloader protocol description 24.5.3.1 physical layer the uart u sed to tr a nsmit inform a tion h a s the following config u r a tion: ?ch a r a cter: 8 -bit d a t a ?p a rity: none ? s top: 2 bits ? flow control: none ?b au d r a te: au tob au d is performed by the bootlo a der to comp u te the b au d r a te chosen by the host. 76543210 ------lb1lb0 bit number bit mnemonic description 7- reserved do not cle a r this bit. 6- reserved do not cle a r this bit. 5- reserved do not cle a r this bit. 4- reserved do not cle a r this bit. 3- reserved do not cle a r this bit. 2- reserved do not cle a r this bit. 1-0 lb1-0 user memory lock bits s ee t a ble 24-17 program lock bits protection description security level lb0 lb1 1 1 1 no progr a m lock fe a t u res en a bled. 2 0 1 bootlo a der progr a mming of the fl a sh is dis a bled. 3 x 0 sa me a s 2, a lso verify thro u gh bootlo a der progr a mming interf a ce is dis a bled.
206 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.3.2 frame description the s eri a l protocol is b a sed on the intel he x-type records. intel hex records consist of a s cii ch a r a cters u sed to represent hex a decim a l v a l u es a nd a re s u mm a rized below. figure 24-10. intel hex type fr a me ? record m a rk: record m a rk is the st a rt of fr a me. this field m u st cont a in ?:?. ?reclen: reclen specifies the n u mber of bytes of inform a tion or d a t a which follows the record type field of the record. ?lo a d offset: lo a d offset specifies the 16-bit st a rting lo a d offset of the d a t a bytes, therefore this field is u sed only for d a t a progr a m record (see s ection ?bootlo a der comm a nd su mm a ry?). ? record type: record type specifies the comm a nd type. this field is u sed to interpret the rem a ining inform a tion within the fr a me. the encoding for a ll the c u rrent record types is described in s ection ?bootlo a der comm a nd su mm a ry?. ?d a t a /info: d a t a /info is a v a ri a ble length field. it consists of zero or more bytes encoded a s p a irs of hex a decim a l digits. the me a ning of d a t a depends on the record type . ? checks u m: the two?s complement of the 8 -bit bytes th a t res u lt from converting e a ch p a ir of a s cii hex a decim a l digits to one byte of bin a ry, a nd incl u ding the reclen field to a nd incl u ding the l a st byte of the data/info field. therefore, the s u m of a ll the a s cii p a irs in a record a fter converting to bin a ry, from the reclen field to a nd incl u ding the checksum field, is zero. 24.5.4 functional description 24.5.4.1 software security bits (ssb) the ss b protects a ny fl a sh a ccess from bootlo a der comm a nds. the comm a nd "progr a m s oft- w a re s ec u rity bit" c a n only write a higher priority level. there a re three levels of sec u rity: ? level 0: no_security (ffh) this is the def au lt level.from level 0, one c a n write level 1 or level 2. ? level 1: write_security (feh) for this level it is impossible to write in the fl a sh memory, b s b or s bv. the bootlo a der ret u rns ?p? on write a ccess. from level 1, one c a n write only level 2. ? level 2: rd_wr_security (fch) level 2 forbids a ll re a d a nd write a ccesses to/from the fl a sh memory. the bootlo a der ret u rns ?l? on re a d or write a ccess. only a f u ll chip er a se in p a r a llel mode ( u sing a progr a mmer) or i s p comm a nd c a n reset the softw a re sec u rity bits. from level 2, one c a nnot re a d a nd write a nything. record record lo a d d a t a m a rk ?:? reclen offset ty p e or info checks u m 1-byte 1-byte 2-bytes 1-byte n-bytes 1-byte
207 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.4.2 full chip erase the i s p comm a nd "f u ll chip er a se" er a ses a ll u ser fl a sh memory (fills with ffh) a nd sets some bytes u sed by the bootlo a der a t their def au lt v a l u es: ?b s b = ffh ? s bv = fch ? ss b = ffh the f u ll chip er a se does not a ffect the bootlo a der. 24.5.4.3 checksum error when a checks u m error is detected, ?x? is sent followed with cr&lf. 24.5.5 flow description 24.5.5.1 overview an initi a liz a tion step m u st be performed a fter e a ch reset. after microcontroller reset, the boot- lo a der w a its for a n au tob au d seq u ence (see section ?a u tob au d perform a nce? ). after the comm u nic a tion is initi a lized, the protocol depends on the record type req u ested by the host. flip, a softw a re u tility to implement bootlo a der progr a mming with a pc, is a v a il a ble from the atmel web site. 24.5.5.2 communicat ion initialization the host initi a lizes the comm u nic a tion by sending a ?u? ch a r a cter to help the bootlo a der to com- p u te the b au d r a te ( au tob au d). figure 24-11. initi a liz a tion table 24-18. s oftw a re s ec u rity byte beh a vior level 0 level 1 level 2 fl a sh any a ccess a llowed re a d-only a ccess a llowed any a ccess not a llowed f u se bit any a ccess a llowed re a d-only a ccess a llowed any a ccess not a llowed b s b & s bv any a ccess a llowed re a d-only a ccess a llowed any a ccess not a llowed ss bany a ccess a llowed write level 2 a llowed re a d-only a ccess a llowed m a n u f a ct u rer info re a d-only a ccess a llowed re a d-only a ccess a llowed re a d-only a ccess a llowed bootlo a der info re a d-only a ccess a llowed re a d-only a ccess a llowed re a d-only a ccess a llowed er a se block allowed not a llowed not a llowed f u ll chip er a se allowed allowed allowed bl a nk check allowed allowed allowed host bootloader "u" performs a u tob au d init comm u nic a tion if (not received "u") "u" comm u nic a tion opened else s ends b a ck ?u? ch a r a cte
208 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.5.3 autobaud performance the bootlo a der fe a t u re a llows a wide r a nge of b au d r a tes in the u ser a pplic a tion. it is a lso a d a pt- a ble to a wide r a nge of oscill a tor freq u encies. this is a ccomplished by me a s u ring the bit-time of a single bit in a received ch a r a cter. this inform a tion is then u sed to progr a m the b au d r a te in terms of timer co u nts b a sed on the oscill a tor freq u ency. the bootlo a der fe a t u re req u ires th a t a n initi a l ch a r a cter ( a n u pperc a se u) be sent to the at 8 9lp51rb2/rc2/ic2 to est a blish the b au d r a te. t a ble 24-19 shows the au tob au d c a p a bility. for at 8 9lp51ic2 the bootlo a der a lw a ys u ses o s ca. if the device boots on o s cb, the boot- lo a der will en a ble a nd switch to o s ca. in this c a se both the o s ca a nd o s cb so u rces m u st be oper a tion a l, i.e. a cryst a l or extern a l clock so u rce m u st be connected to the oscill a tor inp u ts u nless the oscill a tor so u rce w a s previo u sly config u red a s the intern a l rc oscill a tor. table 24-19. a u tob au d perform a nce frequency (mhz) baudrate (khz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728 2400 ok ok ok ok ok ok ok ok ok 4 8 00 ok - okokokokokokok 9600 ok - okokokokokokok 19200 ok - okokok - - okok 3 8 400 - - ok ok - ok ok ok 57600 ----ok---ok 115200 --------ok frequency (mhz) baudrate (khz) 8 10 11.0592 12 14.746 16 20 24 26.6 2400 ok ok ok ok ok ok ok ok ok 4 8 00 ok ok ok ok ok ok ok ok ok 9600 ok ok ok ok ok ok ok ok ok 19200 ok ok ok ok ok ok ok ok ok 3 8 400 - - ok ok ok ok ok ok ok 57600 - - ok - okokokokok 115200 - - ok - ok - - - -
209 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.5.4 command data stream protocol all comm a nds a re sent u sing the s a me flow. e a ch fr a me sent by the host is echoed by the bootlo a der. figure 24-12. comm a nd flow 24.5.6 write/program commands description this flow is common to the following fr a mes: ?fl a sh progr a mming d a t a fr a me ? eof or atmel fr a me (only progr a mming atmel fr a me) ? config byte progr a mming d a t a fr a me ?b au d r a te fr a me figure 24-13. write/progr a m flow bootloader ":" s ends first ch a r a cter of the fr a me if (not received ":") s ends fr a me (m a de of 2 a s cii gets fr a me, a nd s ends b a ck echo for e a ch received byte host else ":" s ends echo a nd s t a rt reception ch a r a cters per byte) echo an a lysis host bootloader write command ?x? & cr & lf no_ s ecurity wait write command checks u m error wait programming s end s ec u rity error s end command_ok s end write comm a nd wait checksum error wait command_ok wait security error or command aborted command finished s end checks u m error command aborted ?p? & cr & lf or ?.? & cr & lf
210 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary example : 24.5.7 blank check command description figure 24-14. bl a nk check flow example: host : 01 0010 00 55 9a bootloader : 01 0010 00 55 9a . cr lf programming data (write 55h at address 0010h in the flash) host : 02 0000 03 05 01 f5 bootloader : 02 0000 03 05 01 f5. cr lf programming atmel function (write ssb to level 2) host : 03 0000 03 06 00 55 9f bootloader : 03 0000 03 06 00 55 9f . cr lf writing frame (write bsb to 55h) host bootloader blank check command ?x? & cr & lf fl a sh bl a nk wait blank check command s end first address s end command_ok s end bl a nk check comm a nd wait checksum error wait address not erased wait command_ok or command aborted command finished s end checks u m error command finished ?.? & cr & lf or address & cr & lf not er a sed checks u m error host : 05 0000 04 0000 7fff 01 78 bootloader : 05 0000 04 0000 7fff 01 78 . cr lf blank check ok bootloader : 05 0000 04 0000 7fff 01 70 x cr lf cr lf blank check with checksum error host : 05 0000 04 0000 7fff 01 70 bootloader : 05 0000 04 0000 7fff 01 78 xxxx cr lf blank check ok at address xxxx host : 05 0000 04 0000 7fff 01 78
211 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.8 display data description figure 24-15. displ a y flow example: host bootloader display command ?x? & cr & lf rd_wr_ s ecurity wait display command read data s end s ec u rity error s end displ a y d a t a s end displ a y comm a nd wait checksum error wait display data wait security error or command aborted command finished s end checks u m error command aborted ?l? & cr & lf or "address = " all d a t a re a d complet fr a me "reading value" cr & lf all d a t a re a d all d a t a re a d command finished checks u m error host : 05 0000 04 0000 0020 00 d7 bootloader : 05 0000 04 0000 0020 00 d7 cr lf bootloader 0000=-----d a t a ------ cr lf (16 d a t a ) bootloader 0010=-----d a t a ------ cr lf (16 d a t a ) bootloader 0020=d a t a cr lf ( 1 d a t a ) display data from address 0000h to 0020h
212 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.9 read function description this flow is simil a r for the following fr a mes: ?re a ding fr a me ? eof fr a me/ atmel fr a me (only re a ding atmel fr a me) figure 24-16. re a d flow example : host bootloader read command ?x? & cr & lf rd_wr_ s ecurity wait read command read value s end s ec u rity error s end d a t a re a d s end re a d comm a nd wait checksum error wait value of data wait security error or command aborted command finished s end checks u m error command aborted ?l? & cr & lf or ?value? & ?.? & cr & lf checks u m error host : 02 0000 05 07 02 f0 bootloader : 02 0000 05 07 02 f0 v a l u e . cr lf host : 02 0000 01 02 00 fb bootloader : 02 0000 01 02 00 fb v a l u e . cr lf re a d f u nction (re a d s bv) atmel re a d f u nction (re a d bootlo a der version)
213 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.5.10 bootloader command summary note: 1. at 8 9c51ic2 only. this byte differs from at 8 9c51ic2, which u ses 02h table 24-20. bootlo a der comm a nd su mm a ry command command name data[0] data[1] command effect 00h progr a m code progr a m nb code byte. bootlo a der will a ccept u p to 12 8 ( 8 0h) d a t a bytes. the d a t a bytes sho u ld be 12 8 byte p a ge fl a sh bo u nd a ry. 03h write f u nction 01h 00h er a se block0 (0000h-1fffh) 20h er a se block1 (2000h-3fffh) 40h er a se block2 (4000h-7fffh) 8 0h er a se block3 ( 8 000h- bfffh) c0h er a se block4 (c000h- ffffh) 03h 00h h a rdw a re reset 04h 00h er a se s bv & b s b 05h 00h progr a m ss b level 1 01h progr a m ss b level 2 06h 00h progr a m b s b (v a l u e to write in d a t a [2]) 01h progr a m s bv (v a l u e to write in d a t a [2]) 07h - f u ll chip er a se (this comm a nd needs a bo u t 6 sec to be exec u ted) 0ah 10h (1) progr a m o s c f u se (v a l u e to write in d a t a [2]) 04h progr a m bljb f u se (v a l u e to write in d a t a [2]) 0 8 hprogr a m x2 f u se (v a l u e to write in d a t a [2]) 04h displ a y f u nction d a t a [0:1] = st a rt a ddress d a t a [2:3] = end a ddress d a t a [4] = 00h:displ a y code d a t a [4] = 01h: bl a nk check displ a y code bl a nk check 05h re a d f u nction 00h 00h m a n u f a ct u rer id 01h device id #1 02h device id #2 03h device id #3 07h 00h re a d ss b 01h re a d b s b 02h re a d s bv 06h re a d extr a byte 0bh 00h re a d h a rdw a re byte 0eh 00h re a d device boot id1 01h re a d device boot id2 0fh 00h re a d bootlo a der version
214 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.6 in-system programming (isp) the atmel at 8 9lp51rb2/rc2/ic2 microcontroller fe a t u res 64k bytes of on-chip in- s ystem progr a mm a ble fl a sh progr a m memory a nd 4k bytes of nonvol a tile eprom d a t a memory. in- s ystem progr a mming a llows progr a mming a nd reprogr a mming of the microcontroller positioned inside the end system. using a simple 4-wire s pi interf a ce, the progr a mmer comm u nic a tes seri- a lly with the at 8 9lp51rb2/rc2/ic2 microcontroller, reprogr a mming a ll nonvol a tile memories on the chip. in- s ystem progr a mming elimin a tes the need for physic a l remov a l of the chips from the system. this will s a ve time a nd money, both d u ring development in the l a b, a nd when u pd a t- ing the softw a re or p a r a meters in the field. the progr a mming interf a ce of the at 8 9lp51rb2/rc2/ic2 incl u des the following fe a t u res: ?fo u r-wire seri a l s pi progr a mming interf a ce or 12-pin p a r a llel interf a ce ? s elect a ble pol a rity reset entry into progr a mming ?user s ign a t u re arr a y ?flexible p a ge progr a mming ?row er a se c a p a bility ?p a ge write with a u to-er a se comm a nds ?progr a mming s t a t u s register for more det a iled inform a tion on in- s ystem progr a mming, refer to the applic a tion note entitled ?at 8 9lp in- s ystem progr a mming s pecific a tion?. 24.6.1 physical interface the at 8 9lp51rb2/rc2/ic2 provides a st a nd a rd progr a mming comm a nd set with two physic a l interf a ces: a bit-seri a l a nd a byte-p a r a llel interf a ce. norm a l fl a sh progr a mming u tilizes the s eri a l peripher a l interf a ce ( s pi) pins of a n at 8 9lp51rb2/rc2/ic2 microcontroller. the s pi is a f u ll- d u plex synchrono u s seri a l interf a ce consisting of fo u r wires: s eri a l clock ( s ck), m a ster- in/ s l a ve-o u t (mi s o), m a ster-o u t/ s l a ve-in (mo s i) a nd s l a ve s elect ( ss ). when progr a mming a n at 8 9lp51rb2/rc2/ic2 device, the progr a mmer a lw a ys oper a tes a s the s pi m a ster, a nd the t a rget system a lw a ys oper a tes a s the s pi sl a ve. to enter or rem a in in progr a mming mode the device?s reset line (r s t) m u st be held a ctive. with the a ddition of vdd a nd gnd, a n at 8 9lp51rb2/rc2/ic2 microcontroller c a n be progr a mmed with a minim u m of eight connec- tions a s shown in fig u re 24-17 . figure 24-17. in- s ystem progr a mming device connections at 8 9lp51rd2/ed2/id2 vdd r s t p1.7/ s ck p1.5/mo s i gnd s eri a l clock s eri a l in r s t p1.4/ ss p1.6/mi s o s eri a l o u t ss pol gnd or vdd
215 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary the p a r a llel interf a ce is a speci a l mode of the seri a l interf a ce, i.e. the seri a l interf a ce is u sed to en a ble the p a r a llel interf a ce. after en a bling the interf a ce seri a lly over p1.7/ s ck a nd p1.5/mo s i, p1.5 is reconfig u red a s a n a ctive-low o u tp u t en a ble (oe ) for d a t a on port 0. when oe =1, com- m a nd, a ddress a nd write d a t a bytes a re inp u t on port 0 a nd s a mpled a t the rising edge of s ck. when oe =0, re a d d a t a bytes a re o u tp u t on port 0 a nd sho u ld be s a mpled on the f a lling edge of s ck. the p1.7/ s ck a nd r s t pins contin u e to f u nction in the s a me m a nner. with the a ddition of vdd a nd gnd, the p a r a llel interf a ce req u ires a minim u m of fo u rteen connections a s shown in fig u re 24-1 8 . note th a t a connection to p1.6/mi s o is not req u ired for u sing the p a r a llel interf a ce. figure 24-18. p a r a llel progr a mming device connections the progr a mming interf a ce is a me a ns of extern a lly progr a mming the at 8 9lp51rb2/rc2/ic2 microcontroller. the interf a ce c a n be u sed to progr a m the device both in-system a nd in a st a nd- a lone seri a l progr a mmer. the interf a ce does not req u ire a ny clock other th a n s ck a nd is not limited by the system clock freq u ency. d u ring progr a mming the system clock so u rce of the t a r- get device c a n oper a te norm a lly. when designing a system where in- s ystem progr a mming will be u sed, the following observ a - tions m u st be considered for correct oper a tion: ?the i s p interf a ce u ses the s pi clock mode 0 (cpol = 0, cpha = 0) excl u sively with a m a xim u m freq u ency of 5 mhz. ?the at 8 9lp51rb2/rc2/ic2 will enter progr a mming mode only when its reset line (r s t) is a ctive. to simplify this oper a tion, it is recommended th a t the t a rget reset c a n be controlled by the in- s ystem progr a mmer. to a void problems, the in- s ystem progr a mmer sho u ld be a ble to keep the entire t a rget system reset for the d u r a tion of the progr a mming cycle. the t a rget system sho u ld never a ttempt to drive the three s pi lines while reset is a ctive. ?the i s p en a ble f u se m u st be set to a llow progr a mming d u ring a ny reset period. if the i s p f u se is dis a bled, i s p m a y only be entered a t por. to enter progr a mming the r s t pin m u st be driven a ctive prior to the end of power-on reset (por). after por h a s completed the device will rem a in in i s p mode u ntil r s t is bro u ght in a ctive. once the initi a l i s p session h a s ended, the power to the t a rget device m u st be cycled off a nd on to enter a nother session. note th a t if this method is req u ired, a n a ctive-low reset pol a rity is recommended. ?for st a nd a lone progr a mmers, a n a ctive-low reset pol a rity is recommended (pol = 0). r s t m a y then be tied directly to gnd to ens u re correct entry into progr a mming mode reg a rdless of the device settings. at 8 9lp51rd2/ed2/id2 vdd r s t p1.7/ s ck p1.5/mo s i gnd clock oe r s t p1.4/ ss ss p0.7-0 d a t a in/o u t 8 pol gnd or vdd
216 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.6.2 command format progr a mming comm a nds consist of two pre a mble bytes, a n opcode byte, two a ddress bytes, a nd zero or more d a t a bytes. fig u re 24-19 on p a ge 216 shows a simplified flow ch a rt of a com- m a nd seq u ence. a s a mple comm a nd p a cket is shown in fig u re 24-20 on p a ge 217 . the ss pin defines the p a cket fr a me. ss m u st be bro u ght low before the first byte in a comm a nd is sent a nd bro u ght b a ck high a fter the fin a l byte in the comm a nd h a s been sent. the comm a nd is not complete u ntil ss ret u rns high. comm a nd bytes a re iss u ed seri a lly on mo s i. d a t a o u tp u t bytes a re received seri a lly on mi s o. p a ckets of v a ri a ble length a re s u pported by ret u rning ss high when the fin a l req u ired byte h a s been tr a nsmitted. in some c a ses comm a nd bytes h a ve a don?t c a re v a l u e. don?t c a re bytes in the middle of a p a cket m u st be tr a nsmitted. don?t c a re bytes a t the end of a p a cket m a y be ignored. p a ge oriented instr u ctions a lw a ys incl u de a f u ll 16-bit a ddress. the higher order bits select the p a ge a nd the lower order bits select the byte within th a t p a ge. the at 8 9lp51rb2/rc2/ic2 a llo- c a tes 6 bits for byte a ddress, 1 bit for low/high h a lf p a ge selection a nd 9 bits for p a ge a ddress. the h a lf p a ge to be a ccessed is a lw a ys fixed by the p a ge a ddress a nd h a lf select a s tr a nsmitted. the byte a ddress specifies the st a rting a ddress for the first d a t a byte. after e a ch d a t a byte h a s been tr a nsmitted, the byte a ddress is incremented to point to the next d a t a byte. this a llows a p a ge comm a nd to line a rly sweep the bytes within a p a ge. if the byte a ddress is incremented p a st the l a st byte in the h a lf p a ge, the byte a ddress will roll over to the first byte in the s a me h a lf p a ge. while lo a ding bytes into the p a ge b u ffer, overwriting previo u sly lo a ded bytes will res u lt in d a t a corr u ption. for a s u mm a ry of a v a il a ble comm a nds, see t a ble 24-21 on p a ge 21 8 . figure 24-19. comm a nd s eq u ence flow ch a rt inp u t pre a mble 2 (55h) inp u t opcode inp u t address high byte inp u t address low byte inp u t/o u tp u t d a t a address +1 inp u t pre a mble 1 (aah)
217 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-20. i s p comm a nd p a cket ( s eri a l) figure 24-21. i s p comm a nd p a cket (p a r a llel) 70 654321 7 0 654321 7 0 654321 7 0 654321 70 654321 ss s ck mo s i mi s o pre a mble 2 opcode address high address low d a t a in d a t a o u t x xxx pre a mble 1 x ss s ck p0 55h opcode address high address low aah d a t a in oe write p0 55h opcode address high address low aah d a t a o u t oe read
218 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. progr a m en a ble m u st be the first comm a nd iss u ed a fter entering into progr a mming mode. 2. p a r a llel en a ble switches the interf a ce from seri a l to p a r a llel form a t u ntil r s t ret u rns high. 3. any n u mber of d a t a bytes from 1 to 64 m a y be written/re a d. the intern a l a ddress is incremented between e a ch byte. 4. e a ch byte a ddress selects one f u se or lock bit. d a t a bytes m u st be 00h or ffh. 5. s ee t a ble 24-5 on p a ge 1 88 for f u se definitions. 6. s ee t a ble 24-6 on p a ge 190 for lock bit definitions. 7. symbol key : table 24-21. progr a mming comm a nd su mm a ry command opcode addr high addr low data 0 data n progr a m en a ble (1) 1010 1100 0101 0011 ? ? ? p a r a llel en a ble (2) 1010 1100 0011 0101 ? ? ? chip er a se 1000 1010 ???? re a d s t a t u s 0110 0000 xxxx x xxx xxxx xxxx s t a t u s o u t lo a d p a ge b u ffer (3) 0101 0001 xxxx xxxx 00bb bbbb d a t a in 0 ... d a t a in n write code p a ge (3) 0101 0000 aaaa aaaa a sbb bbbb d a t a in 0 ... d a t a in n write code p a ge with a u to-er a se (3) 0111 0000 aaaa aaaa a sbb bbbb d a t a in 0 ... d a t a in n re a d code p a ge (3) 0011 0000 aaaa aaaa a sbb bbbb d a t a o u t 0 ... d a t a o u t n write d a t a p a ge (3) 1101 0000 000 a aaaa a sbb bbbb d a t a in 0 ... d a t a in n write d a t a p a ge with a u to-er a se (3) 1101 0010 000 a aaaa a sbb bbbb d a t a in 0 ... d a t a in n re a d d a t a p a ge (3) 1011 0000 000 a aaaa a sbb bbbb d a t a o u t 0 ... d a t a o u t n write user f u ses (3)(4)(5) 1110 0001 0000 0000 00bb bbbb d a t a in 0 ... d a t a in n write user f u ses with a u to-er a se (3)(4)(5) 1111 0001 0000 0000 00bb bbbb d a t a in 0 ... d a t a in n re a d user f u ses (3)(4)(5) 0110 0001 0000 0000 00bb bbbb d a t a o u t 0 ... d a t a o u t n write lock bits (3)(4)(6) 1110 0100 0000 0000 00bb bbbb d a t a in 0 ... d a t a in n re a d lock bits (3)(4)(6) 0110 0100 0000 0000 00bb bbbb d a t a o u t 0 ... d a t a o u t n write user s ign a t u re p a ge (3) 0101 0010 0000 0000 a sbb bbbb d a t a in 0 ... d a t a in n write user s ign a t u re p a ge with a u to-er a se (3) 0111 0010 0000 0000 a sbb bbbb d a t a in 0 ... d a t a in n re a d user s ign a t u re p a ge (3) 0011 0010 0000 0000 a sbb bbbb d a t a o u t 0 ... d a t a o u t n re a d atmel s ign a t u re p a ge (3) 0011 1000 0000 0000 0sbb bbbb d a t a o u t 0 ... d a t a o u t n a :p a ge address bit s: h a lf p a ge s elect bit b: byte address bit x: don?t c a re bit
219 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 24.6.3 status register the c u rrent st a te of the memory m a y be a ccessed by re a ding the st a t u s register. the st a t u s reg- ister is shown in t a ble 24-22 . 24.6.4 data polling the at 8 9lp51rb2/rc2/ic2 implements data polling to indic a te the end of a progr a mming cycle. while the device is b u sy, a ny a ttempted re a d of the l a st byte written will ret u rn the d a t a byte with the m s b complemented. once the progr a mming cycle h a s completed, the tr u e v a l u e will be a ccessible. d u ring er a se the d a t a is a ss u med to be ffh a nd data polling will ret u rn 7fh. when writing m u ltiple bytes in a p a ge, the data v a l u e will be the l a st d a t a byte lo a ded before progr a mming begins, not the written byte with the highest physic a l a ddress within the p a ge. 24.6.5 programming interface timing this section det a ils gener a l system timing seq u ences a nd constr a ints for entering or exiting in- s ystem progr a mming a s well a s p a r a meters rel a ted to the s eri a l peripher a l interf a ce d u ring i s p. the gener a l timing p a r a meters for the following w a veform fig u res a re listed in section ?tim- ing p a r a meters? on p a ge 222 . 24.6.5.1 power-up sequence exec u te this seq u ence to enter progr a mming mode immedi a tely a fter power- u p. in the r s t pin is dis a bled or if the i s p f u se is dis a bled, this is the only method to enter progr a mming (see ?extern a l reset? on p a ge 53 ). 1. apply power between vdd a nd gnd pins. r s t sho u ld rem a in low. 2. w a it a t le a st t pwrup . a nd drive r s t high if a ctive-high otherwise keep low. 3. w a it a t le a st t s ut for the intern a l power-on reset to complete. the v a l u e of t s ut will depend on the c u rrent settings of the device. 4. s t a rt progr a mming session. table 24-22. s t a t u s register ? ??? load s ucce ss wrtinh bu s y bit76543210 symbol function load lo a d fl a g. cle a red low by the lo a d p a ge b u ffer comm a nd a nd set high by the next memory write. this fl a g sign a ls th a t the p a ge b u ffer w a s previo u sly lo a ded with d a t a by the lo a d p a ge b u ffer comm a nd. s ucce ss su ccess fl a g. cle a red low a t the st a rt of a progr a mming cycle a nd will only be set high if the progr a mming cycle completes witho u t interr u ption from the browno u t detector. wrtinh write inhibit fl a g. cle a red low by the browno u t detector (bod) whenever progr a mming is inhibited d u e to v dd f a lling below the minim u m req u ired progr a mming volt a ge. if a bod episode occ u rs d u ring progr a mming, the s ucce ss fl a g will rem a in low a fter the cycle is complete. bu s y b u sy fl a g. cle a red low whenever the memory is b u sy progr a mming or if write is c u rrently inhibited.
220 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-22. s eri a l progr a mming power- u p s eq u ence 24.6.5.2 power-down sequence exec u te this seq u ence to power-down the device after progr a mming. 1. drive s ck low. 2. w a it a t le a st t ss d a nd trist a te mo s i. 3. w a it a t le a st t rhz a nd drive r s t low. 4. w a it a t le a st t ss z a nd trist a te s ck. 5. w a it no more th a n t pwrdn a nd power off vdd. figure 24-23. s eri a l progr a mming power-down s eq u ence 24.6.5.3 isp start sequence exec u te this seq u ence to exit cpu exec u tion mode a nd enter i s p mode when the device h a s p a ssed power-on reset a nd is a lre a dy oper a tion a l. 1. drive r s t high. 2. w a it t rlz + t s tl . 3. drive s ck low. 4. s t a rt progr a mming session. v dd r s t ss s ck high z mi s o high z mo s i t pwrup t por + t s ut t z ss v dd r s t ss s ck high z mi s o high z mo s i t pwrdn t ss d t ss z
221 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-24. in- s ystem progr a mming (i s p) s t a rt s eq u ence 24.6.5.4 isp exit sequence exec u te this seq u ence to exit i s p mode a nd res u me cpu exec u tion mode. 1. drive s ck low. 1. w a it a t le a st t ss d . 2. trist a te mo s i. 3. w a it a t le a st t rhz a nd bring r s t low. 4. w a it t ss z a nd trist a te s ck. figure 24-25. in- s ystem progr a mming (i s p) exit s eq u ence note: the w a veforms on this p a ge a re not to sc a le. 24.6.5.5 serial peripheral interface the s eri a l peripher a l interf a ce ( s pi) is a byte-oriented f u ll-d u plex synchrono u s seri a l comm u ni- c a tion ch a nnel. d u ring in- s ystem progr a mming, the progr a mmer a lw a ys a cts a s the s pi m a ster a nd the t a rget device a lw a ys a cts a s the s pi sl a ve. the t a rget device receives seri a l d a t a on mo s i a nd o u tp u ts seri a l d a t a on mi s o. the progr a mming interf a ce implements a st a nd a rd s pi port with a fixed d a t a order a nd for in- s ystem progr a mming, bytes a re tr a nsferred m s b first a s shown in fig u re 24-26 . the s ck ph a se a nd pol a rity follow s pi clock mode 0 (cpol = 0, cpha = 0) where bits a re s a mpled on the rising edge of s ck a nd o u tp u t on the f a lling edge of s ck. for more det a iled timing inform a tion see fig u re 24-27 . t s tl v dd r s t ss s ck high z mo s i high z mi s o xtal1 t rlz t z ss t ss e v dd r s t ss s ck high z mo s i high z mi s o xtal1 t ss z t ss d t rhz
222 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 24-26. i s p byte s eq u ence figure 24-27. s eri a l progr a mming interf a ce timing figure 24-28. p a r a llel progr a mming interf a ce timing 24.6.6 timing parameters the timing p a r a meters for fig u re 24-22 , fig u re 24-23 , fig u re 24-24 , fig u re 24-25 , fig u re 24-27 a nd fig u re 24-2 8 a re shown in t a ble . 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 mo s i mi s o s ck d a t a sa mpled t sr t sse t slsh t sov t sf t sox t ssd t sck t shsl t soe t soh t sih t sis ss sck miso mosi t sr t sse t slsh t sf t pox t ssd t sck t shsl t pov t poe t pih t pis ss sck p0 oe t poh
223 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary note: 1. t s ck is independent of t clcl . table 24-23. progr a mming interf a ce timing p a r a meters symbol parameter min max units t clcl s ystem clock cycle time 0 60 ns t pw rup power on to ss high time 10 s t por power-on reset time 100 s t pw rdn ss tr i s t a te to power off 1 s t rlz r s t low to i/o trist a te t clcl 2 t clcl ns t s tl r s t low s ettling time 100 ns t rhz r s t high to ss tr i s t a te 0 2 t clcl ns t s ck s eri a l clock cycle time 200 (1) ns t s h s l clock high time 75 ns t s l s h clock low time 50 ns t s r rise time 25 ns t s f f a ll time 25 ns t s i s s eri a l inp u t s et u p time 10 ns t s ih s eri a l inp u t hold time 10 ns t s oh s eri a l o u tp u t hold time 10 ns t s ov s eri a l o u tp u t v a lid time 35 ns t pi s p a r a llel inp u t s et u p time 10 ns t pih p a r a llel inp u t hold time 10 ns t poh p a r a llel o u tp u t hold time 10 ns t pov p a r a llel o u tp u t v a lid time 35 ns t s oe s eri a l o u tp u t en a ble time 10 ns t s ox s eri a l o u tp u t dis a ble time 25 ns t poe p a r a llel o u tp u t en a ble time 10 ns t pox p a r a llel o u tp u t dis a ble time 25 ns t ss e ss active le a d time t s l s h ns t ss d ss in a ctive l a g time t s l s h ns t z ss s ck s et u p to ss low 25 ns t ss z s ck hold a fter ss high 25 ns t w r write cycle time 2.5 ms t aw r write cycle with a u to-er a se time 5 ms t er s chip er a se cycle time 7.5 ms
224 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary
225 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25. electrical characteristics notes: 1. under ste a dy st a te (non-tr a nsient) conditions, i ol m u st be extern a lly limited a s follows: m a xim u m i ol per port pin: 10 ma m a xim u m tot a l i ol for a ll o u tp u t pins: 15 ma if i ol exceeds the test condition, v ol m a y exceed the rel a ted specific a tion. pins a re not g ua r a nteed to sink c u rrent gre a ter th a n the listed test conditions. 2. minim u m v dd for power-down is 2v. 3. all ch a r a cteristics cont a ined in this d a t a sheet a re b a sed on sim u l a tion a nd ch a r a cteriz a tion of other microcontrollers m a n u - f a ct u red in the s a me process technology. these v a l u es a re prelimin a ry v a l u es representing design t a rgets, a nd will be u pd a ted a fter ch a r a cteriz a tion of a ct ua l silicon. 25.1 absolute maximum ratings* oper a ting temper a t u re ................................... -40c to + 8 5c *notice: s tresses beyond those listed u nder ?absol u te m a xim u m r a tings? m a y c au se perm a nent d a m- a ge to the device. this is a stress r a ting only a nd f u nction a l oper a tion of the device a t these or a ny other conditions beyond those indic a ted in the oper a tion a l sections of this specific a tion is not implied. expos u re to a bsol u te m a xim u m r a ting conditions for extended periods m a y a ffect device reli a bility. s tor a ge temper a t u re ..................................... -65c to +150c volt a ge on any pin with respect to gro u nd......-0.7v to +5.5v m a xim u m oper a ting volt a ge ............................................ 5.5v dc o u tp u t c u rrent...................................................... 15.0 ma 25.2 dc characteristics t a = -40c to 8 5c, v dd = 2.4v to 5.5v ( u nless otherwise noted) symbol parameter condition min max units v il inp u t low-volt a ge -0.5 0.2 v dd - 0.1 v v ih inp u t high-volt a ge 0.2 v dd + 0.9 v dd + 0.5 v v ol o u tp u t low-volt a ge (1) i ol = 10 ma, v dd = 2.7v, t a = 8 5c 0.5 v v oh o u tp u t high-volt a ge with we a k p u ll- u ps en a bled i oh = - 8 0 a, v dd = 3v 10% 2.4 v i oh = -30 a 0.75 v dd v i oh = -12 a 0.9 v dd v v oh1 o u tp u t high-volt a ge with s trong p u ll- u ps en a bled i oh = -10 ma, t a = 8 5c 0.9 v dd i oh = -5 ma, t a = 8 5c 0.75 v dd i il logic 0 inp u t c u rrent v in = 0.45v -50 a i tl logic 1 to 0 tr a nsition c u rrent v in = 2v, v dd = 5v 10% -750 a i li inp u t le a k a ge c u rrent 0 < v in < v dd 10 a r r s t reset p u ll- u p resistor 50 150 k c io pin c a p a cit a nce test freq. = 1 mhz, t a = 25c 10 pf i cc power su pply c u rrent active mode, 12 mhz, v dd = 5.5v 7 ma idle mode, 12 mhz, v dd = 5.5v p1.0 & p1.1 = 0v or v dd 3ma power-down mode (2) v dd = 5.5v, p1.0 & p1.1 = 0v or v dd 5a v dd = 3v, p1.0 & p1.1 = 0v or v dd 2a
226 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.3 typical characteristics the following ch a rts show typic a l beh a vior. these fig u res a re not tested d u ring m a n u f a ct u ring. all c u rrent cons u mption me a s u rements a re performed with a ll i/o pins config u red a s q ua si-bidi- rection a l (with intern a l p u ll- u ps). a sq ua re w a ve gener a tor with r a il-to-r a il o u tp u t is u sed a s a n extern a l clock so u rce for cons u mption vers u s freq u ency me a s u rements. 25.3.1 supply current (internal oscillator) figure 25-1. active su pply c u rrent vs. vcc ( 8 .0 mhz intern a l oscill a tor) figure 25-2. idle su pply c u rrent vs. vcc ( 8 .0 mhz intern a l oscill a tor) 2.4 2.7 3.0 3.3 3.6 3.5 4.0 4.5 5.0 5.5 6.0 6.5 85c -40c 25c vcc (v) icc (ma) active supp l y current vs. vcc 8mhz internal oscillator 2.4 2.7 3.0 3.3 3.6 1.00 1.25 1.50 1.75 2.00 85c -40c 25c vcc (v) icc (ma) idle supply current vs. vcc 8mhz internal oscillator
227 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.3.2 supply current (external clock) figure 25-3. active su pply c u rrent vs. freq u ency figure 25-4. idle su pply c u rrent vs. freq u ency note: all ch a r a cteristics cont a ined in this d a t a sheet a re b a sed on sim u l a tion a nd ch a r a cteriz a tion of other microcontrollers m a n u f a ct u red in the s a me process technology. these v a l u es a re prelimi- n a ry v a l u es representing design t a rgets, a nd will be u pd a ted a fter ch a r a cteriz a tion of a ct ua l silicon. 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 5.5 v 5.0 v 4.5 v 3.6 v 3.0 v 2.4 v frequency (mhz) icc (ma) active supply current vs. frequency external clock source 0 5 10 15 20 25 0 1 2 3 4 5 6 7 5.5 v 5.0 v 4.5 v 3.6 v 3.0 v 2.4 v frequency (mhz) icc (ma) idle supply current vs. frequency external clock source
228 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.4 clock characteristics the v a l u es shown in this t a ble a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. figure 25-5. extern a l clock drive w a veform table 25-1. extern a l clock p a r a meters symbol parameter v dd = 2.4v to 5.5v v dd = 4.5v to 5.5v units min max min max 1/t clcl oscill a tor freq u ency 020025mhz t clcl clock period 50 40 ns t chcx extern a l clock high time 12 ns t clcx extern a l clock low time 12 ns t clch extern a l clock rise time 5 ns t chcl extern a l clock f a ll time 5 ns table 25-2. clock ch a r a cteristics symbol parameter condition min max units f xtal cryst a l oscill a tor freq u ency low power oscill a tor 0 12 mhz high power oscill a tor 0 24 mhz f rc intern a l oscill a tor freq u ency t a = 25c; v dd = 5.0v 7.92 8 .0 8 mhz v dd = 2.4 to 5.5v 7. 8 0 8 .20 mhz
229 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 25-6. typic a l intern a l oscill a tor freq u ency vs. vcc 25.5 reset characteristics the v a l u es shown in this t a ble a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. 25.6 external memory characteristics the v a l u es shown in this t a ble a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. under oper- a ting conditions, lo a d c a p a cit a nce for port 0, ale a nd p s en = 100 pf; lo a d c a p a cit a nce for a ll other o u tp u ts = 8 0 pf. p a r a meters refer to fig u re 25-7 , fig u re 25- 8 a nd fig u re 25-9 . 2.4 2.7 3.0 3.3 3.6 7.80 7.85 7.90 7.95 8.00 8.05 8.10 -40c 0c 25c 70c 85c vcc (v) frequency (mhz) table 25-3. reset ch a r a cteristics symbol parameter condition min max units r r s t reset p u ll- u p resistor 50 150 k v por power-on reset threshold 1.3 1.6 v v bod brown-o u t detector threshold 1.9 2.2 v v bh brown-o u t detector hysteresis 200 300 mv t por power-on reset del a y 135 150 s t w dtr s t w a tchdog reset p u lse width 49t clcl ns table 25-4. extern a l progr a m a nd d a t a memory ch a r a cteristics symbol parameter compatibility mode (1) fast mode (1) units min max min max 1/t clcl oscill a tor freq u ency 024024mhz t lhll ale p u lse width t clcl - d t clcl - d (4) ns t avll address v a lid to ale low 0.5t clcl - d (2) 0.5t clcl - d (2) ns t llax address hold a fter ale low 0.5t clcl - d (3) 0.5t clcl - d (3) ns t lliv ale low to v a lid instr u ction in 2t clcl - d 2t clcl - d ns t llpl ale low to p s en low 0.5t clcl - d (2) 0.5t clcl - d (2) ns t plph p s en p u lse width 1.5t clcl - d (2) 1.5t clcl - d (2) ns
230 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary notes: 1. comp a tibility mode timing for movx a lso a pplies to f a st mode d u ring exetern a l exec u tion of movx. 2. this a ss u mes 50% clock d u ty cycle. the h a lf period depends on the clock high v a l u e t chcx (high d u ty cycle). 3. this a ss u mes 50% clock d u ty cycle. the h a lf period depends on the clock low v a l u e t clcx (low d u ty cycle). 4. in some c a ses p a r a meter t lhll m a y h a ve a minim u m of 0.5t clcl d u ring f a st mode extern a l exec u tion with di s ale = 0. 5. the strobe p u lse width m a y be lengthened by 1, 2 or 3 a ddition a l t clcl u sing w a it st a tes. figure 25-7. extern a l progr a m memory re a d cycle t pliv p s en low to v a lid instr u ction in 1.5t clcl - d (2) 1.5t clcl - d (2) ns t pxix inp u t instr u ction hold a fter p s en 00ns t pxiz inp u t instr u ction flo a t a fter p s en 0.5t clcl - d (2) 0.5t clcl - d (2) ns t pxav p s en to address v a lid 0.5t clcl - d (2) 0.5t clcl - d (2) ns t aviv address to v a lid instr u ction in 2.5t clcl - d (2) 2.5t clcl - d (2) ns t plaz p s en low to address flo a t1010ns t rlrh rd p u lse width (5) 3t clcl - d t clcl - d ns t wlwh wr p u lse width (5) 3t clcl - d t clcl - d ns t rldv rd low to v a lid d a t a in 2.5t clcl - d t clcl - d ns t rhdx d a t a hold a fter rd 00ns t rhdz d a t a flo a t a fter rd t clcl - d t clcl - d ns t lldv ale low to v a lid d a t a in 4t clcl - d 2t clcl - d ns t avdv address to v a lid d a t a in 4.5t clcl - d (2) 2.5t clcl - d (2) ns t llwl ale low to rd or wr low 1.5t clcl - d 1.5t clcl + d t clcl - d t clcl + d ns t avwl address to rd or wr low 2t clcl - d (2) 1.5t clcl - d (2) ns t qvwx d a t a v a lid to wr tr a nsition 1t clcl - d (2) 0.5t clcl - d (2) ns t qvwh d a t a v a lid to wr high 4t clcl - d (2) 1.5t clcl - d (2) ns t whqx d a t a hold a fter wr 1t clcl - d (3) 0.5t clcl - d (3) ns t rlaz rd low to address flo a t-1t clcl + d (2) -0.5t clcl + d (2) ns t whax address hold a fter rd or wr high 1t clcl - d (3) 0.5t clcl - d (3) ns t whlh rd or wr high to ale high 0.5t clcl - d 0.5t clcl + d t clcl - d ns table 25-4. extern a l progr a m a nd d a t a memory ch a r a cteristics t lhll t lliv t pliv t llax t pxiz t plph t plaz t pxav t avll t llpl t aviv t pxix ale psen port 0 port 2 a8 - a15 a0 - a7 a0 - a7 a8 - a15 instr in
231 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 25-8. extern a l d a t a memory re a d cycle figure 25-9. extern a l d a t a memory write cycle 25.7 serial peripheral interface timing the v a l u es shown in these t a bles a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. table 25-5. s pi master ch a r a cteristics symbol parameter min max units t clcl oscill a tor period 41.6 ns t s ck s eri a l clock cycle time 4t clcl ns t s h s l clock high time t s ck /2 - 25 ns t s l s h clock low time t s ck /2 - 25 ns t s r rise time 25 ns t s f f a ll time 25 ns t s i s s eri a l inp u t s et u p time 10 ns t lhll ale data i n a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 rd port 0 port 2 t llwl t rlrh t avll t llax t rlaz t rhdz t avwl t whlh t whax t avdv t lldv t rldv t rhdx t lhll ale data out a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 wr port 0 port 2 t llwl t wlwh t avll t llax t qvwx t qvwh t whqx t avwl t whlh t whax
232 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 25-10. s pi m a ster timing (cpha = 0) t s ih s eri a l inp u t hold time 10 ns t s oh s eri a l o u tp u t hold time 10 ns t s ov s eri a l o u tp u t v a lid time 35 ns table 25-5. s pi master ch a r a cteristics symbol parameter min max units table 25-6. s pi slave ch a r a cteristics symbol parameter min max units t clcl oscill a tor period 41.6 ns t s ck s eri a l clock cycle time 4t clcl ns t s h s l clock high time 1.5 t clcl - 25 ns t s l s h clock low time 1.5 t clcl - 25 ns t s r rise time 25 ns t s f f a ll time 25 ns t s i s s eri a l inp u t s et u p time 10 ns t s ih s eri a l inp u t hold time 10 ns t s oh s eri a l o u tp u t hold time 10 ns t s ov s eri a l o u tp u t v a lid time 35 ns t s oe o u tp u t en a ble time 10 ns t s ox o u tp u t dis a ble time 25 ns t ss e s l a ve en a ble le a d time 10 ns t ss d s l a ve dis a ble l a g time 0 ns ss sck (cpol = 0) sck (cpol = 1) miso mosi t sr t sck t slsh t slsh t shsl t shsl t soh t sf t sis t sih t sov
233 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary figure 25-11. s pi s l a ve timing (cpha = 0) figure 25-12. s pi m a ster timing (cpha = 1) figure 25-13. s pi s l a ve timing (cpha = 1) t sr t sse t slsh t shsl t sov t sf t sox t ssd t sck t slsh t shsl t soe t soh t sih t sis ss sck (cpol = 0) sck (cpol= 1) miso mosi t shsl t slsh t shsl t slsh t sck t soh t sf t sr t sis t sov t sih ss sck (cpol = 0) sck (cpol = 1) miso mosi ss sck (cpol = 0) sck (cpol = 1) miso mosi t sck t sse t shsl t shsl t slsh t slsh t ssd t sih t sis t soe t sov t soh t sox t sf t sr
234 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.8 two-wire serial in terface characteristics t a ble 25-7 describes the req u irements for devices connected to the two-wire s eri a l b u s. the at 8 9lp51rb2/rc2/ic2 two-wire s eri a l interf a ce meets or exceeds these req u irements u nder the noted conditions. the v a l u es shown in this t a ble a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. timing symbols refer to fig u re 25-14 . notes: 1. in at 8 9lp51rb2/rc2/ic2, this p a r a meter is ch a r a cterized a nd not 100% tested. 2. req u ired only for f s cl > 100 khz. table 25-7. two-wire s eri a l b u s req u irements symbol parameter condition min max units v il inp u t low-volt a ge -0.5 0.3 v dd v v ih inp u t high-volt a ge 0.7 v dd v dd + 0.5 v v hys (1) hysteresis of s chmitt trigger inp u ts 0.05 v dd (2) ?v v ol (1) o u tp u t low-volt a ge 3 ma sink c u rrent 0 0.4 v t r (1) rise time for both s da a nd s cl 20 + 0.1c b (3)(2) 300 ns t of (1) o u tp u t f a ll time from v ihmin to v ilm a x 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns t s p (1) s pikes su ppressed by inp u t filter 0 50 (2) ns i i inp u t c u rrent e a ch i/o pin 0.1v dd < v i < 0.9v dd -10 10 a c i (1) c a p a cit a nce for e a ch i/o pin ? 10 pf f s cl s cl clock freq u ency f ck (4) > 16f s cl 0 400 khz rp v a l u e of p u ll- u p resistor f s cl 100 khz f s cl > 100 khz t hd; s ta hold time (repe a ted) s tart condition f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t low low period of the s cl clock f s cl 100 khz 4.7 ? s f s cl > 100 khz 1.3 ? s t high high period of the s cl clock f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t s u; s ta s et- u p time for a repe a ted s tart condition f s cl 100 khz 4.7 ? s f s cl > 100 khz 0.6 ? s t hd;dat d a t a hold time f s cl 100 khz 0 3.45 s f s cl > 100 khz 0 0.9 s t s u;dat d a t a set u p time f s cl 100 khz 250 ? ns f s cl > 100 khz 100 ? ns t s u; s to s et u p time for s top condition f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t buf b u s free time between a s top a nd s ta rt condition f s cl 100 khz 4.7 ? s v dd 0.4v ? 3ma ---------------------------- - 1000ns c b ------------------- ? 3ma ---------------------------- - 300ns c b --------------- -
235 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 3. c b = c a p a cit a nce of one b u s line in pf. 4. f ck = cpu clock freq u ency figure 25-14. two-wire s eri a l b u s timing figure 25-15. s hift register mode timing w a veform t s u; s ta t low t high t low t of t hd; s ta t hd;dat t s u;dat t s u; s to t buf s cl s da t r 25.9 serial port timing : shift register mode the v a l u es in this t a ble a re v a lid for v dd = 2.4v to 5.5v a nd lo a d c a p a cit a nce = 8 0 pf. symbol parameter smod1 = 0 smod1 = 1 units min max min max t xlxl s eri a l port clock cycle time 4t clcl -15 2t clcl -15 s t qvxh o u tp u t d a t a s et u p to clock rising edge 3t clcl -15 t clcl -15 ns t xhqx o u tp u t d a t a hold a fter clock rising edge t clcl -15 t clcl -15 ns t xhdx inp u t d a t a hold a fter clock rising edge 0 0 ns t xhdv inp u t d a t a v a lid to clock rising edge 15 15 ns 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 0 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 1
236 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.10 dual analog compar ator characteristics the v a l u es shown in this t a ble a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. figure 25-16. an a log reference volt a ge typic a l ch a r a cteristics 25.11 dadc characteristics the v a l u es shown in these t a bles a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nless otherwise noted. table 25-8. d ua l an a log comp a r a tor ch a r a cteristics symbol parameter condition min max units v cm common mode inp u t volt a ge gnd v dd v v o s inp u t offset volt a ge v dd = 3.6v 20 mv v aref an a log reference volt a ge 1.23 1.36 v v ref reference delt a volt a ge 90 120 mv t cmp comp a r a tor prop a g a tion del a yv in+ ? v in- = 20mv; v dd = 2.4v 200 ns t aref reference s ettling time 3 s table 25-9. adc ch a r a cteristics symbol parameter conditi on min typical max units resol u tion 10 bits absol u te acc u r a cy (incl u ding inl, dnl, q ua ntiz a tion error, g a in a nd offset error) 4l s b integr a l non-line a rity (inl) 4 l s b differenti a l non-line a rity (dnl) 4l s b 2.4 2.7 3.0 3.3 3.6 1.1 1.2 1.3 1.4 1.5 vref+ 85c vref+ 25c vref+ -40c vref 85c vref 25c vref -40c vref- -40c vref- 25c vref- 85c vcc (v) v ref (v)
237 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary . g a in error 16 l s b offset error 16 l s b t ack clock period 500 ns t adc conversion time 13t ack 14t ack + 2t clcl ns v ref reference volt a ge extern a l reference v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v intern a l reference 0.9 1.0 1.1 v v in s ingle-ended inp u t volt a ge v dd /2 - v ref v dd /2 + v ref v v cmi differenti a l inp u t common mode volt a ge gnd v dd v v di differenti a l inp u t volt a ge 0 v ref v r in an a log inp u t resist a nce 10 k r mux an a log m u x resist a nce 10 k c s /h sa mple & hold c a p a cit a nce 3 pf table 25-10. dac ch a r a cteristics symbol parameter conditi on min typical max units resol u tion 10 bits t ack clock period t ack t clcl 500 ns t dac conversion time 11t ack 12t ack + 2t clcl ns v ref reference volt a ge extern a l reference v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v intern a l reference 0.9 1.0 1.1 v v in s ingle-ended inp u t volt a ge v dd /2 - v ref v dd /2 + v ref v v cmo differenti a l o u tp u t common mode volt a ge v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v v do differenti a l o u tp u t volt a ge 0 v ref v r out an a log o u tp u t resist a nce 100 200 k table 25-9. adc ch a r a cteristics (contin u ed) symbol parameter conditi on min typical max units
238 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.12 test conditions 25.12.1 ac testing input/output waveform (1) note: 1. ac inp u ts d u ring testing a re driven a t v dd - 0.5v for a logic ?1? a nd 0.45v for a logic ?0?. timing me a s u rements a re m a de a t v ih min. for a logic ?1? a nd v il m a x. for a logic ?0?. 25.12.2 float waveform (1) note: 1. for timing p u rposes, a port pin is no longer flo a ting when a 100 mv ch a nge from lo a d volt a ge occ u rs. a port pin begins to flo a t when 100 mv ch a nge from the lo a ded v oh /v ol level occ u rs. 25.12.3 i cc test condition: active mode figure 25-17. connection di a gr a m for i cc active me a s u rement. all other pins a re disconnected for a ctive s u pply c u rrent me a s u rements a ll ports a re config u red in q ua si-bidirection a l mode. timers 0, 1 a nd 2 a re config u red to be free r u nning in their def au lt timer modes. the cpu exe- c u tes a simple r a ndom n u mber gener a tor th a t a ccesses ram, the s fr b u s a nd exercises the alu a nd h a rdw a re m u ltiplier. x t al 2 rst v dd v dd i cc x t al 1 gnd (nc) clock signal v dd pol gnd
239 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 25.12.4 i cc test condition: idle mode figure 25-18. connection di a gr a m for i cc idle me a s u rement. all other pins a re disconnected- all other pins a re disconnected 25.12.5 clock signal waveform for i cc tests figure 25-19. clock s ign a l w a veform for i cc in active a nd idle modes, t clch = t chcl = 5 ns 25.12.6 i cc test condition: power-down mode figure 25-20. connection di a gr a m for i cc power-down me a s u rement.all other pins a re dis- connected, v dd = 2v to 5.5v x t al 2 rst v dd v dd i cc x t al 1 gnd (nc) clock signal v dd gnd pol v cc - 0.5v 0.45v 0.2 v cc - 0.1v 0.7 v cc t chcx t chcx t clch t chcl t clcl xtal2 rst v dd v dd i cc xtal1 gnd (nc) v dd pol gnd
240 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary
241 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 26. ordering information notes: 1. s peed is specified for single-cycle f a st mode with x2 clock 2. s ee t a ble 26-1 on p a ge 242 for a cross reference between at 8 9c51rb2/rc2/ic2 a nd at 8 9lp51rb2/rc2/ic2 26.1 green package op tion (pb/halide-free) supply voltage speed (1) temperature range code flash # oscillators ordering code package packing 2.4v to 5.5v 20 mhz ind u stri a l (-40 c to 8 5 c) 24kb 1 at 8 9lp51rb2-20aau 44aa (lqfp) tr a y at 8 9lp51rb2-20aaur reel at 8 9lp51rb2-20au 44a (tqfp) tr a y at 8 9lp51rb2-20aur reel at 8 9lp51rb2-20ju 44j (plcc) s tick at 8 9lp51rb2-20jur reel at 8 9lp51rb2-20mu 44m1 (vqfn) tr a y at 8 9lp51rb2-20mur reel at 8 9lp51rb2-20pu 40p6 (pdip) s tick 32kb 1 at 8 9lp51rc2-20aau 44aa (lqfp) tr a y at 8 9lp51rc2-20aaur reel at 8 9lp51rc2-20au 44a (tqfp) tr a y at 8 9lp51rc2-20aur reel at 8 9lp51rc2-20ju 44j (plcc) s tick at 8 9lp51rc2-20jur reel at 8 9lp51rc2-20mu 44m1 (vqfn) tr a y at 8 9lp51rc2-20mur reel at 8 9lp51rc2-20pu 40p6 (pdip) s tick 32kb 2 at 8 9lp51ic2-20aau 44aa (lqfp) tr a y at 8 9lp51ic2-20aaur reel at 8 9lp51ic2-20au 44a (tqfp) tr a y at 8 9lp51ic2-20aur reel at 8 9lp51ic2-20ju 44j (plcc) s tick at 8 9lp51ic2-20jur reel at 8 9lp51ic2-20mu 44m1 (vqfn) tr a y at 8 9lp51ic2-20mur reel package types 44aa 44-le a d, very thin pl a stic q ua d fl a t p a ck a ge, 1.2 mm thickness (vqfp/lqfp) 44a 44-le a d, thin pl a stic q ua d fl a t p a ck a ge, 1.0 mm thickness (tqfp) 44j 44-le a d, pl a stic j-le a ded chip c a rrier (plcc) 44m1 44-p a d, 7 x 7 x 1.0 mm body, pl a stic very thin q ua d fl a t no le a d p a ck a ge (vqfn/mlf) 40p6 40-le a d, 0.600? wide, pl a stic d ua l inline p a ck a ge (pdip)
242 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 26.2 cross reference wi th at89c51rb2/rc2/ic2 table 26-1. ordering cross reference at 8 9c51rb2/rc2/ic2 to at 8 9lp51rb2/rc2/ic2 device migration package packing previous ordering code new ordering code at 8 9c51rb2 to at 8 9lp51rb2 plcc44 s tick at 8 9c51rb2- s l s um at 8 9lp51rb2-20ju reel at 8 9c51rb2- s lrum at 8 9lp51rb2-20ju + s l3 8 3 vqfp44 tr a yat 8 9c51rb2-rltum at 8 9lp51rb2-20aau reel at 8 9c51rb2-rlrum at 8 9lp51rb2-20aau + s l3 8 3 at 8 9c51rc2 to at 8 9lp51rc2 plcc44 s tick at 8 9c51rc2- s l s um at 8 9lp51rc2-20ju reel at 8 9c51rc2- s lrum at 8 9lp51rc2-20ju + s l3 8 3 vqfp44 tr a yat 8 9c51rc2-rltum at 8 9lp51rc2-20aau reel at 8 9c51rc2-rlrum at 8 9lp51rc2-20aau + s l3 8 3 at 8 9c51ic2 to at 8 9lp51ic2 plcc44 s tick at 8 9c51ic2- s l s um at 8 9lp51ic2-20ju reel at 8 9c51ic2- s lrum at 8 9lp51ic2-20ju + s l3 8 3 vqfp44 tr a yat 8 9c51ic2-rltum at 8 9lp51ic2-20aau reel at 8 9c51ic2-rlrum at 8 9lp51ic2-20aau + s l3 8 3 table 26-2. p a ck a ges not fo u nd in at 8 9c51rb2/rc2/ic2 device package packing ordering code at 8 9c51rb2 to at 8 9lp51rb2 tqfp44 tr a yat 8 9lp51rd2-20au reel at 8 9lp51rd2-20aur vqfn44 tr a yat 8 9lp51rd2-20mu reel at 8 9lp51rd2-20mur at 8 9c51rc2 to at 8 9lp51rc2 tqfp44 tr a yat 8 9lp51ed2-20au reel at 8 9lp51ed2-20aur vqfn44 tr a yat 8 9lp51ed2-20mu reel at 8 9lp51ed2-20mur at 8 9c51ic2 to at 8 9lp51ic2 tqfp44 tr a yat 8 9lp51id2-20au reel at 8 9lp51id2-20aur vqfn44 tr a yat 8 9lp51id2-20mu reel at 8 9lp51id2-20mur
243 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 27. packaging information 27.1 44aa ? vqfp/lqfp 2 3 25 orchard parkway san jo s e, ca 951 3 1 title drawing no. r rev. 44aa, 44-lead, 10 x 10 mm body size, 1.4 mm body thickne ss , 0.8 mm lead pitch, low profile pla s tic quad flat package (vqfp) b 44aa 10/5/2001 pin 1 identifier 0~8 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of mea s ure = mm) s ymbol min nom max note note s : 1. thi s package conform s to jedec reference ms-026, variation acb. 2. dimen s ion s d1 and e1 do not include mold protru s ion. allowa b le protru s ion i s 0.25 mm per s ide. dimen s ion s d1 and e1 are maximum pla s tic b ody s ize dimen s ion s including mold mi s match. 3 . lead coplanarity i s 0.102 mm maximum. a ? ? 1.60 a1 0.05 ? 0.15 a2 0.95 1.40 1.05 d 11.9 12.00 12.10 d1 9.90 10.00 10.10 note 2 e 11.9 12.00 12.10 e1 9.90 10.00 10.10 note 2 b 0. 3 0 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
244 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 27.2 44a ? tqfp 0~7 l c a1 a2 a d e b bottom view side view top view e1 d1 e common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
245 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 27.3 44j ? plcc notes: 1. this p a ck a ge conforms to jedec reference m s -01 8 , v a ri a tion ac. 2. dimensions d1 a nd e1 do not incl u de mold protr u sion. allow a ble protr u sion is .010"(0.254 mm) per side. dimension d1 a nd e1 incl u de mold mism a tch a nd a re me a s u red a t the extreme m a teri a l condition a t the u pper or lower p a rting line. 3. le a d copl a n a rity is 0.004" (0.102 mm) m a xim u m. a 4.191 ? 4.572 a1 2.2 8 6 ? 3.04 8 a2 0.50 8 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.9 8 6 ? 16.002 b 0.660 ? 0. 8 13 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of me a s u re = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.31 8 (0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-le a d, pl a stic j-le a ded chip c a rrier (plcc) b 44j 10/04/01 2325 orch a rd p a rkw a y sa n jose, ca 95131 title drawing no. r rev.
246 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 27.4 44m1 ? vqfn/mlf title drawing no. gpc rev. packa g e drawin g contact: packagedrawing s @atmel.com 44m1 zws h 44m1, 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, 5.20 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimen s ion s (unit of mea s ure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a 3 0.20 ref b 0.18 0.2 3 0. 3 0 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd- 3 . top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a 3 a seating plane pin #1 triangle pin #1 chamfer (c 0. 3 0) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
247 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 27.5 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
248 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary 28. revision history revision no. history revision a ? october 2011 ? initi a l rele a se
i 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 44-le a d tqfp/lqfp ..........................................................................................2 1.2 44-le a d plcc ....................................................................................................2 ................... ................. ................ ................ ................. ................ ............... 3 1.3 44-p a d vqfn/qfn/mlf ....................................................................................3 1.4 40-pin pdip .......................................................................................................3 1.5 pin description ..................................................................................................4 2 overview ............ ................ ................ ............... .............. .............. ............ 6 2.1 block di a gr a m ................................................................................................... 8 2.2 s ystem config u r a tion ........................................................................................ 8 2.3 comp a rison to the atmel at 8 9c51rb2/rc2/ic2 ...........................................10 3 memory organization ......... .............. ............... .............. .............. .......... 13 3.1 progr a m memory .............................................................................................13 3.2 intern a l d a t a memory ......................................................................................16 3.3 extern a l d a t a memory .....................................................................................17 3.4 extr a ram (edata) ........................................................................................22 3.5 extended s t a ck ...............................................................................................23 4 special function registers ..... ................ ................. ................ ............. 24 5 enhanced cpu ............. ................. ................ ................. .............. .......... 31 5.1 f a st mode ........................................................................................................31 5.2 comp a tibility mode ..........................................................................................32 5.3 m u ltiply?acc u m u l a te unit (mac) .....................................................................32 5.4 enh a nced d ua l d a t a pointers .........................................................................35 5.5 instr u ction s et extensions ...............................................................................39 6 system clock ............. ................ ................. ................ ................. .......... 41 6.1 cryst a l oscill a tor a ..........................................................................................42 6.2 extern a l clock s o u rce a ..................................................................................43 6.3 intern a l rc oscill a tor ......................................................................................43 6.4 cryst a l oscill a tor b (at 8 9lp51ic2) ................................................................43 6.5 extern a l clock s o u rce b (at 8 9lp51ic2) ........................................................44 6.6 d ua l oscill a tor su pport (at 8 9lp51ic2) ..........................................................44
ii 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table of contents (continued) 6.7 x1/x2 fe a t u re .................................................................................................46 6. 8s ystem clock presc a ler ..................................................................................47 6.9 peripher a l clocks ............................................................................................4 8 6.10 timer su bclock (at 8 9l51ic2) ........................................................................50 7 reset ............. ................ ................. ................ ................. .............. .......... 51 7.1 power-on reset ...............................................................................................51 7.2 brown-o u t reset ..............................................................................................52 7.3 extern a l reset .................................................................................................53 7.4 h a rdw a re w a tchdog reset .............................................................................54 7.5 pca w a tchdog reset ......................................................................................54 7.6 s oftw a re reset ................................................................................................54 8 power saving modes .......... .............. ............... .............. .............. .......... 55 8 .1 idle mode .........................................................................................................55 8 .2 power-down mode ...........................................................................................56 8 .3 red u cing power cons u mption ........................................................................57 8 .4 low power config u r a tion ................................................................................5 8 9 interrupts ........ ................. ................ ................. .............. .............. .......... 59 9.1 interr u pt priority ...............................................................................................59 9.2 interr u pt response ..........................................................................................61 9.3 interr u pt registers ...........................................................................................63 10 external interrupts .......... ................ ................. .............. .............. .......... 66 11 keyboard interface and g eneral-purpose interrupts .. .............. .......... 66 11.1 registers .........................................................................................................6 8 12 i/o ports ............... ................ .............. ............... .............. .............. .......... 69 12.1 port config u r a tion ............................................................................................69 12.2 port an a log f u nctions .....................................................................................72 12.3 port re a d-modify-write ...................................................................................73 12.4 port altern a te f u nctions ..................................................................................73 13 enhanced timer 0 and timer 1 with pwm .. ................. .............. .......... 77 13.1 registers .........................................................................................................7 8 13.2 mode 0 ? v a ri a ble width timer/co u nter ......................................................... 8 0 13.3 mode 1 ? 16-bit a u to-relo a d timer/co u nter ................................................... 8 1
iii 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table of contents (continued) 13.4 mode 2 ? 8 -bit a u to-relo a d timer/co u nter ..................................................... 8 2 13.5 mode 3 ? 8 -bit s plit timer ............................................................................... 8 2 13.6 p u lse width mod u l a tion ................................................................................... 8 3 14 timer 2 ................. ................ .............. ............... .............. .............. .......... 87 14.1 timer 2 registers ............................................................................................ 8 9 14.2 c a pt u re mode ..................................................................................................90 14.3 a u to-relo a d mode ...........................................................................................91 14.4 b au d r a te gener a tor ......................................................................................93 14.5 freq u ency gener a tor (progr a mm a ble clock o u t) ...........................................94 15 programmable counter array (pca) .............. .............. .............. .......... 95 15.1 pca timer/co u nter .........................................................................................95 15.2 pca mod u les ...................................................................................................9 8 15.3 pca c a pt u re mode .......................................................................................101 15.4 16-bit s oftw a re timer/ comp a re mode .........................................................101 15.5 high s peed o u tp u t mode ..............................................................................102 15.6 p u lse width mod u l a tor mode ........................................................................103 15.7 pca w a tchdog timer ....................................................................................104 16 hardware watchdog timer ... ................ ................. ................ ............. 104 16.1 s oftw a re reset ..............................................................................................105 16.2 wdt registers ..............................................................................................106 17 serial interface (uart ) .............. ................. ................ .............. ........... 107 17.1 m u ltiprocessor comm u nic a tions ...................................................................109 17.2 b au d r a tes ....................................................................................................109 17.3 fr a ming error detection ................................................................................114 17.4 a u tom a tic address recognition ....................................................................114 17.5 more abo u t mode 0 .......................................................................................116 17.6 more abo u t mode 1 .......................................................................................120 17.7 more abo u t modes 2 a nd 3 ...........................................................................122 18 enhanced serial peripheral interface ....... ................ .............. ........... 125 1 8 .1 interf a ce description ......................................................................................126 1 8 .2 m a ster oper a tion ...........................................................................................129 1 8 .3 s l a ve oper a tion .............................................................................................129 1 8 .4 error conditions .............................................................................................130
iv 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table of contents (continued) 1 8 .5 s eri a l clock timing ........................................................................................131 1 8 .6 registers .......................................................................................................132 19 two-wire serial inte rface .................... .............. .............. ............ ........ 134 19.1 d a t a tr a nsfer a nd fr a me form a t ..................................................................135 19.2 m u lti-m a ster b u s s ystems, arbitr a tion a nd s ynchroniz a tion .........................137 19.3 overview of the twi mod u le .........................................................................139 19.4 register overview .........................................................................................141 19.5 using the twi ................................................................................................142 19.6 tr a nsmission modes .....................................................................................144 20 dual analog comparators ..... ................ ................. ................ ............. 157 20.1 an a log inp u t m u xes .......................................................................................15 8 20.2 intern a l reference volt a ge ............................................................................159 20.3 comp a r a tor interr u pt debo u ncing .................................................................159 21 digital-to-analog/analog-to-digital c onverter ................ .................. 164 21.1 adc oper a tion ..............................................................................................166 21.2 temper a t u re s ensor ......................................................................................167 21.3 dac oper a tion ..............................................................................................167 21.4 clock s election ..............................................................................................16 8 21.5 s t a rting a conversion ....................................................................................169 21.6 noise consider a tions ....................................................................................169 21.7 registers .......................................................................................................170 22 instruction set summary ... .............. ............... .............. .............. ........ 173 22.1 instr u ction s et extensions .............................................................................177 23 on-chip debug system ...... .............. ............... .............. .............. ........ 183 23.1 physic a l interf a ce ..........................................................................................1 8 3 23.2 s oftw a re bre a kpoints ....................................................................................1 8 4 23.3 limit a tions of on-chip deb u g .......................................................................1 8 4 24 flash memory programming .... ................. ................ .............. ........... 185 24.1 memory org a niz a tion ....................................................................................1 8 6 24.2 user config u r a tion f u ses ..............................................................................1 88 24.3 fl a sh h a rdw a re s ec u rity ...............................................................................1 8 9 24.4 in-applic a tion progr a mming (iap) .................................................................190 24.5 bootlo a der .....................................................................................................199
v 3722a?micro?10/11 at89lp51rb2/rc2/ic2 preliminary table of contents (continued) 24.6 in- s ystem progr a mming (i s p) .......................................................................214 25 electrical characteristics ... .............. ............... .............. .............. ........ 225 25.1 absol u te m a xim u m r a tings* .........................................................................225 25.2 dc ch a r a cteristics .........................................................................................225 25.3 typic a l ch a r a cteristics ..................................................................................226 25.4 clock ch a r a cteristics .....................................................................................22 8 25.5 reset ch a r a cteristics ....................................................................................229 25.6 extern a l memory ch a r a cteristics ...................................................................229 25.7 s eri a l peripher a l interf a ce timing .................................................................231 25. 8 two-wire s eri a l interf a ce ch a r a cteristics ......................................................234 25.9 s eri a l port timing: s hift register mode ........................................................235 25.10 d ua l an a log comp a r a tor ch a r a cteristics ......................................................236 25.11 dadc ch a r a cteristics ....................................................................................236 25.12 test conditions ..............................................................................................23 8 26 ordering information .......... .............. ............... .............. .............. ........ 241 26.1 green p a ck a ge option (pb/h a lide-free) ........................................................241 26.2 cross reference with at 8 9c51rb2/rc2/ic2 ..............................................242 27 packaging information .......... ................ ................. ................ ............. 243 27.1 44aa ? vqfp/lqfp ......................................................................................243 27.2 44a ? tqfp ...................................................................................................244 27.3 44j ? plcc ...................................................................................................245 27.4 44m1 ? vqfn/mlf .......................................................................................246 27.5 40p6 ? pdip ..................................................................................................247 28 revision history ....... ................ ................ ................. ................ ........... 248 table of contents.......... ................. ................ ................. ................ ........... i
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